powerpc/t4240: set pcie liodn in the correct register

The liodn for the T4240's PCIE controller is no longer set
through a register in the guts register block but with one
in the PCIE register block

powerpc/t4240: set pcie liodn in the correct register

The liodn for the T4240's PCIE controller is no longer set
through a register in the guts register block but with one
in the PCIE register block itself.
Use the already existing SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>

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powerpc/t1040: Update defines to support T1040SoC personalities

T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced

powerpc/t1040: Update defines to support T1040SoC personalities

T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced personality of T1040 with less cores(2 cores)
-T1022:Reduced personality of T1040 with 2 cores and without L2 switch

Update defines in arch/powerpc header files, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefiles]
Acked-by: York Sun <yorksun@freescale.com>

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MPC824x: remove obsolete "PN62" board

The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade. It is now
causing build issues

MPC824x: remove obsolete "PN62" board

The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade. It is now
causing build issues. Instead of wasting time on things nobody is
interested in any more, we rather drop this board.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@grandegger.com>
cc: Tom Rini <trini@ti.com>

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include: delete include/linux/config.h

Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This com

include: delete include/linux/config.h

Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

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powerpc: convert makefiles to Kbuild style

Note:
arch/powerpc/cpu/mpc8260/Makefile is originally like follows:

---<snip>---
START = start.o kgdb.o
COBJS = traps.o serial_smc.o seria

powerpc: convert makefiles to Kbuild style

Note:
arch/powerpc/cpu/mpc8260/Makefile is originally like follows:

---<snip>---
START = start.o kgdb.o
COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
---<snip>---
COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o
---<snip>---
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)

The link rule `$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)'
is weird.
kbdg.o is not included in $(OBJS) but linked into $(LIB)
and $(LIB) is not dependent on kgdb.o.
(Broken dependency tracking)

So,
START = start.o kgdb.o
shoud have been
START = start.o
SOBJS = kgdb.o

That is why this commit adds kgdb.o to obj-y, not to extra-y.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>

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fsl/mpc85xx: define common serdes_clock_to_string function

This allows to share some common code for the boards that use a corenet
base SoC.

Two different versions of the function are available in

fsl/mpc85xx: define common serdes_clock_to_string function

This allows to share some common code for the boards that use a corenet
base SoC.

Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix t1040qds.c]
Acked-by: York Sun <yorksun@freescale.com>

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mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it

If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be

mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it

If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.

This was successfuly tested on kmp204x board with some MT41K128M16 DDR3
RAM chips (no module used, chips directly soldered on board with an SPD
EEPROM).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix minor conflicts in fsl_ddr_dimm_params.h,
lc_common_dimm_params.c, common_timing_params.h]
Acked-by: York Sun <yorksun@freescale.com>

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mpc8xxx: call i2c_set_bus_num in __get_spd

This is necessary with the new I2C subystem that was introduced lately.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

powerpc/usb:Differentiate USB controller base address

Introduce different macros for storing addresses of multiple
USB controllers. This is required for successful initialization
and usage of multip

powerpc/usb:Differentiate USB controller base address

Introduce different macros for storing addresses of multiple
USB controllers. This is required for successful initialization
and usage of multiple USB controllers inside u-boot

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

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powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs

CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is de

powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs

CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is defined for all 85xx socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-usb

usb: add enum usb_init_type parameter to usb_lowlevel_init

This parameter will later be used to verify OTG ports.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

powerpc/mpc85xx: Add workaround for erratum A006379

Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to

powerpc/mpc85xx: Add workaround for erratum A006379

Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.

Erratum A006379 applies to
T4240 rev 1.0
B4860 rev 1.0, 2.0

Signed-off-by: York Sun <yorksun@freescale.com>

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powerpc: Fix CamelCase warnings in DDR related code

Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized

powerpc: Fix CamelCase warnings in DDR related code

Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>

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powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator

CHASSIS2 architecture never fix clock groups for Cluster and hardware
accelerator like PME, FMA. These are SoC defined. SoC define

powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator

CHASSIS2 architecture never fix clock groups for Cluster and hardware
accelerator like PME, FMA. These are SoC defined. SoC defines :-
- NUM of PLLs present in the system
- Clusters and their Clock group
- hardware accelerator and their clock group
if no clock group, then platform clock divider for FMAN, PME

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

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powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2

CHASSIS2 architecture never defines type of L2 cache present in SoC.
it is dependent upon the core present in the SoC.
for example,
-

powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2

CHASSIS2 architecture never defines type of L2 cache present in SoC.
it is dependent upon the core present in the SoC.
for example,
- e6500 core has L2 cluster (Kibo)
- e5500 core has Backside L2 Cache

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

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Coding Style cleanup: replace leading SPACEs by TABs

Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>

Coding Style cleanup: remove trailing white space

Signed-off-by: Wolfgang Denk <wd@denx.de>

SPDX: fix IBM-pibs license identifier

The SPDX License List version 1.19 now contains an official entry for
the IBM-pibs license. However, instead of our suggestion "ibm-pibs",
the SPDX License Lis

SPDX: fix IBM-pibs license identifier

The SPDX License List version 1.19 now contains an official entry for
the IBM-pibs license. However, instead of our suggestion "ibm-pibs",
the SPDX License List uses "IBM-pibs", with the following rationale:
"The reason being that all other SPDX License List short identifiers
tend towards using capital letters unless spelling a word. I'd prefer
to be consistent to this end".

Change the license IDs to use the official name.

Signed-off-by: Wolfgang Denk <wd@denx.de>

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powerpc/mpc85xx: Add workaround for erratum A-005125

In a very rare condition, a system hang is possible when the e500 core
initiates a guarded load to PCI / PCIe /SRIO performs a coherent write
to

powerpc/mpc85xx: Add workaround for erratum A-005125

In a very rare condition, a system hang is possible when the e500 core
initiates a guarded load to PCI / PCIe /SRIO performs a coherent write
to memory. Please refer to errata document for more details. This erratum
applies to the following SoCs and their variants, if any.

BSC9132
BSC9131
MPC8536
MPC8544
MPC8548
MPC8569
MPC8572
P1010
P1020
P1021
P1022
P1023
P2020
C29x

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Scott Wood <scottwood@freescale.com>

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powerpc/mpc85xx: Fix the I2C bus speed error on p1022

The source clock frequency of I2C bus on p1022 is the platform(CCB)
clock, not CCB/2. The wrong source clock frequency leads to wrong
I2C bus sp

powerpc/mpc85xx: Fix the I2C bus speed error on p1022

The source clock frequency of I2C bus on p1022 is the platform(CCB)
clock, not CCB/2. The wrong source clock frequency leads to wrong
I2C bus speed setting. so, fixed it.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>

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SPL: P1022DS: switch to new multibus/multiadapter support

- Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
- Use the function i2c_init_all instead of i2c_init

Signed-off-by:

SPL: P1022DS: switch to new multibus/multiadapter support

- Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
- Use the function i2c_init_all instead of i2c_init

Signed-off-by: Ying Zhang <b40530@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Fix for incorrect conversion hex string to number (FMAN firmware address).

Signed-off-by: Николай Пузанов <punzik@gmail.com>
Acked-by: York Sun <yorksun@freescale.com>

powerpc/sec: Add workaround for SEC A-003571

Multiple read/write transactions initiated by security
engine may cause system to hang.
Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.

Signed-off-by

powerpc/sec: Add workaround for SEC A-003571

Multiple read/write transactions initiated by security
engine may cause system to hang.
Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

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