| 550650dd | 20-Sep-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Use common NS16550 driver for PPC4xx UART
This patch removes the PPC4xx UART driver. Instead the common NS16550
driver is used, since all PPC4xx SoC's use this peripheral device.
The file 4
ppc4xx: Use common NS16550 driver for PPC4xx UART
This patch removes the PPC4xx UART driver. Instead the common NS16550
driver is used, since all PPC4xx SoC's use this peripheral device.
The file 4xx_uart.c now only implements the UART clock calculation
function which also sets the SoC internal UART divisors.
All PPC4xx board config headers are changed to use this common NS16550
driver now.
Tested on these boards:
acadia, canyonlands, katmai, kilauea, sequoia, zeus
Signed-off-by: Stefan Roese <sr@denx.de>
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| afabb498 | 12-Sep-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Big header cleanup part 2, mostly PPC405 related
This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way t
ppc4xx: Big header cleanup part 2, mostly PPC405 related
This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.
As a part from this cleanup, the GPIO definitions for PPC405EP are
corrected. The high and low parts of the registers (for example
CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in
the wrong order. This patch now fixes this issue by switching these
xxxH and xxxL values. This brings the GPIO 405EP port in sync with all
other PPC4xx ports.
Signed-off-by: Stefan Roese <sr@denx.de>
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| 5e7abce9 | 11-Sep-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Big header cleanup, mostly PPC440 related
This patch starts a bit PPC4xx header cleanup. First patch mostly
touches PPC440 files. A later patch will touch the PPC405 files as well.
This cle
ppc4xx: Big header cleanup, mostly PPC440 related
This patch starts a bit PPC4xx header cleanup. First patch mostly
touches PPC440 files. A later patch will touch the PPC405 files as well.
This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.
Signed-off-by: Stefan Roese <sr@denx.de>
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| 09887762 | 16-Sep-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Move gpio.h to ppc4xx-gpio.h since its ppc4xx specific
Signed-off-by: Stefan Roese <sr@denx.de> |
| b36df561 | 09-Sep-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Move ppc4xx headers to powerpc include directory
This patch moves some ppc4xx related headers from the common include
directory (include/) to the powerpc specific one
(arch/powerpc/include/a
ppc4xx: Move ppc4xx headers to powerpc include directory
This patch moves some ppc4xx related headers from the common include
directory (include/) to the powerpc specific one
(arch/powerpc/include/asm/). This way to common include directory is not
so cluttered with files.
Signed-off-by: Stefan Roese <sr@denx.de>
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| 8a805df1 | 16-Sep-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx/fdt/flash: Change fdt_fixup_nor_flash_node() to not rely on cs size
This patch changes the behaviour of the fdt_fixup_nor_flash_node()
function. Now it doesn't patch the size of the "reg" pro
ppc4xx/fdt/flash: Change fdt_fixup_nor_flash_node() to not rely on cs size
This patch changes the behaviour of the fdt_fixup_nor_flash_node()
function. Now it doesn't patch the size of the "reg" property with the
chip-select size, but with the size returned from the new function
flash_get_bank_size(). This function will return per weak default the
flash size of the bank (bank = chip-select numer) detected by the flash
driver. If this does not fit your needs, this function may be overridden
by a board specific one.
For this the parameters needed to be changed. So I intentionally squashed
the PPC4xx stuff using this routine into this patch. Otherwise it would
not be git-bisectable anymore.
The board specific function for the AMCC/APM Ebony eval board is now
included in this patch version.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Detlev Zundel <dzu@denx.de>
Cc: Gerald Van Baren <vanbaren@cideas.com>
Cc: Wolfgang Denk <wd@denx.de>
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| e69e520f | 01-Sep-2010 |
Timur Tabi <timur@freescale.com> |
fsl: refactor MPC8610 and MPC5121 DIU code to use existing bitmap and logo features
The Freescale MPC8610 and MPC5121 DIU code had re-implement two features that already
existed in U-Boot: bitmap dr
fsl: refactor MPC8610 and MPC5121 DIU code to use existing bitmap and logo features
The Freescale MPC8610 and MPC5121 DIU code had re-implement two features that already
existed in U-Boot: bitmap drawing and top-of-screen logo (CONFIG_VIDEO_LOGO).
So delete the 8610-specific code and use the built-in features instead.
Signed-off-by: Timur Tabi <timur@freescale.com>
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| 800eb096 | 20-Sep-2010 |
Michael Zaidman <michael.zaidman@gmail.com> |
POST cleanup.
- Revives POST for blackfin arch;
- Removes redundant code:
arch/blackfin/lib/post.c
arch/powerpc/cpu/ppc4xx/commproc.c
arch/powerpc/cpu/mpc512x/common.c
- fixes up the
POST cleanup.
- Revives POST for blackfin arch;
- Removes redundant code:
arch/blackfin/lib/post.c
arch/powerpc/cpu/ppc4xx/commproc.c
arch/powerpc/cpu/mpc512x/common.c
- fixes up the post_word_{load|store} usage.
Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com>
Acked-by: Detlev Zundel <dzu@denx.de>
Tested-by: Anatolij Gustschin <agust@denx.de>
List of the maintainers of the affected by patch boards:
Cc: Stephan Linz <linz@li-pro.net>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Niklaus Giger <niklaus.giger@netstal.com>
Cc: Larry Johnson <lrj@acm.org>
Cc: Feng Kan <fkan@amcc.com>
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| 40e74c85 | 18-Aug-2010 |
Wolfgang Denk <wd@denx.de> |
bedbug_860.c, bedbug_603e.c: Fix return type to silence compile warnings.
commit 47e26b1b "cmd_usage(): simplify return code handling" caused
the following compile warnings:
bedbug_860.c: In functi
bedbug_860.c, bedbug_603e.c: Fix return type to silence compile warnings.
commit 47e26b1b "cmd_usage(): simplify return code handling" caused
the following compile warnings:
bedbug_860.c: In function 'bedbug860_do_break':
bedbug_860.c:73: warning: 'return' with a value, in function returning void
bedbug_860.c:121: warning: 'return' with a value, in function returning void
Fix the return type.
Actually these files could need some cleanup - commands should
return proper error codes, and there are coding style issues.
=> To be fixed later.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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| c0026fc5 | 07-Sep-2010 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx |
| f3cac538 | 31-Aug-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Invalidate d-cache when used as init-ram
We need to invalidate the data cache after it has been used as init-ram.
This problem was detected on the lwmon5 update.
Signed-off-by: Stefan Roes
ppc4xx: Invalidate d-cache when used as init-ram
We need to invalidate the data cache after it has been used as init-ram.
This problem was detected on the lwmon5 update.
Signed-off-by: Stefan Roese <sr@denx.de>
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| c1ab75c7 | 26-Aug-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Fix 440EPx bug in reconfigure_pll()
This patch fixes a bug in reconfigure_pll(), where the detection of
the current bootstrap option is wrong. The ICS bits where incorrectly
shifted. This bu
ppc4xx: Fix 440EPx bug in reconfigure_pll()
This patch fixes a bug in reconfigure_pll(), where the detection of
the current bootstrap option is wrong. The ICS bits where incorrectly
shifted. This bug was found on the lwmon5 board, which uses bootstrap
option H (I2C bootstrap EEPROM).
Additionally a bit of code was moved into the if statement, since its
only used after later on. No need to run this code all the time.
Also, a few empty lines are added to make the code better readable.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Rupjyoti Sarmah <rsarmah@amcc.com>
Cc: Victor Gallardo <vgallardo@appliedmicro.com>
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| 8d9207c7 | 27-Aug-2010 |
York Sun <yorksun@freescale.com> |
Fix parameters to support RDIMM for P2020DS
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
| b80d3054 | 19-Aug-2010 |
Matthew McClintock <msm@freescale.com> |
mpx85xx/fdt: Add cpu-release-addr for all cores
We currently do not add a cpu-release-addr for core 0, this is needed
when we want to reset core 0 and later restart it from Linux
Signed-off-by: Mat
mpx85xx/fdt: Add cpu-release-addr for all cores
We currently do not add a cpu-release-addr for core 0, this is needed
when we want to reset core 0 and later restart it from Linux
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| ed062e0f | 18-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs
Official docs call it the Job Ring not Job Queue for the p4080 security
block. Match the docs to reduce confusion.
Signed-o
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs
Official docs call it the Job Ring not Job Queue for the p4080 security
block. Match the docs to reduce confusion.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 680c613a | 09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx
fixes breakeage introduced by commit
a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query
feature reporting register for num cores on unk
powerpc/8xxx: share PIC defines among 85xx and 86xx
fixes breakeage introduced by commit
a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query
feature reporting register for num cores on unknown cpus"
Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 5700bb63 | 27-Jul-2010 |
Mike Frysinger <vapier@gentoo.org> |
miiphy: constify device name
The driver name does not need to be writable, so constify it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com> |
| 48690d80 | 20-Jul-2010 |
Heiko Schocher <heiko.schocher@invitel.hu> |
net ppc: fix ethernet device names with spaces
since commit 1384f3bb8a4f9066805b70c1418eda78ecb73fdd ethernet names
with spaces drop a
Warning: eth device name has a space!
message. This patch fix
net ppc: fix ethernet device names with spaces
since commit 1384f3bb8a4f9066805b70c1418eda78ecb73fdd ethernet names
with spaces drop a
Warning: eth device name has a space!
message. This patch fix it for:
- "FEC ETHERNET" devices found on
mpc512x, mpc5xxx, mpc8xx and mpc8220 boards.
renamed to "FEC".
- "SCC ETHERNET" devices found on
mpc8xx, mpc82xx based boards. Renamed to "SCC".
- "HDLC ETHERNET" devices found on mpc8xx boards
Renamed to "HDLC"
- "FCC ETHERNET" devices found on mpc8260 and mpc85xx based
boards. Renamed to "FCC"
Tested on the kup4k board.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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| cdb74977 | 24-Jul-2010 |
Wolfgang Denk <wd@denx.de> |
Rename getenv_r() into getenv_f()
While running from flash, i. e. before relocation, we have only a
limited C runtime environment without writable data segment. In this
phase, some configurations (f
Rename getenv_r() into getenv_f()
While running from flash, i. e. before relocation, we have only a
limited C runtime environment without writable data segment. In this
phase, some configurations (for example with environment in EEPROM)
must not use the normal getenv(), but a special function. This
function had been called getenv_r(), with the idea that the "_r"
suffix would mean the same as in the _r_eentrant versions of some of
the C library functions (for example getdate vs. getdate_r, getgrent
vs. getgrent_r, etc.).
Unfortunately this was a misleading name, as in U-Boot the "_r"
generally means "running from RAM", i. e. _after_ relocation.
To avoid confusion, rename into getenv_f() [as "running from flash"]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
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| a37c36f4 | 15-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus
doing so helps avant garde users, such as those using simulators that
allow users to configure the number of cores, so as
powerpc/8xxx: query feature reporting register for num cores on unknown cpus
doing so helps avant garde users, such as those using simulators that
allow users to configure the number of cores, so as to not have to
manually adjust u-boot sources. h/w should also be reliably setting
FRR NCPU in the future.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 5fb8a8a7 | 02-Jul-2010 |
york <yorksun@freescale.com> |
powerpc/8xxx: Improvement to DDR parameters
Changes for P2020DS DDR applies to other 8xxx platform
Signed-off-by: York Sun <yorksun@freescale.com> |
| 9490ff48 | 02-Jul-2010 |
york <yorksun@freescale.com> |
powerpc/8xxx: Enable DDR3 RDIMM support
Enabled registered DIMMs using data from SPD. RDIMMs have registers
which need to be configured before using. The register configuration
words are stored in S
powerpc/8xxx: Enable DDR3 RDIMM support
Enabled registered DIMMs using data from SPD. RDIMMs have registers
which need to be configured before using. The register configuration
words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
should read those RCWs and put into DDR controller before initialization.
Signed-off-by: York Sun <yorksun@freescale.com>
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| 7fd101c9 | 02-Jul-2010 |
york <yorksun@freescale.com> |
powerpc/8xxx: Enabled address hashing for 85xx
For 85xx silicon which supports address hashing, it can be activated by
hwconfig.
Signed-off-by: York Sun <yorksun@freescale.com> |
| 5800e7ab | 02-Jul-2010 |
york <yorksun@freescale.com> |
powerpc/8xxx: Enable quad-rank DIMMs.
Previous code presumes each DIMM has up to two rank (chip select). Newer
DDR controller supports up to four chip select on one DIMM.
Signed-off-by: York Sun <y
powerpc/8xxx: Enable quad-rank DIMMs.
Previous code presumes each DIMM has up to two rank (chip select). Newer
DDR controller supports up to four chip select on one DIMM.
Signed-off-by: York Sun <yorksun@freescale.com>
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| 076bff8f | 02-Jul-2010 |
york <yorksun@freescale.com> |
powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.
Also check dimm size and ran
powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.
Also check dimm size and rank size for memory controller interleaving
Signed-off-by: York Sun <yorksun@freescale.com>
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