| e93bd4bb | 19-Jul-2022 |
Jon Lin <jon.lin@rock-chips.com> |
rockchip: rv1106: Modify the error correction of EMMC clock drive strength
Only the fspi clk is needed to be set 6mA.
Change-Id: Idaa9384a5f3dc16a3bde417f6fb1c68b9c404349 Signed-off-by: Jon Lin <jo
rockchip: rv1106: Modify the error correction of EMMC clock drive strength
Only the fspi clk is needed to be set 6mA.
Change-Id: Idaa9384a5f3dc16a3bde417f6fb1c68b9c404349 Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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| eba76a1f | 27-May-2022 |
Liang Chen <cl@rock-chips.com> |
rockchip: rv1106: fix reboot error when venc/npu use pvtpll
When venc/npu use pvtpll, reboot will fail, because pvtpll is reset before venc/npu reset, so venc/npu is not completely reset, system wil
rockchip: rv1106: fix reboot error when venc/npu use pvtpll
When venc/npu use pvtpll, reboot will fail, because pvtpll is reset before venc/npu reset, so venc/npu is not completely reset, system will block when access NoC in SPL.
Enable pvtpll can make venc/npu reset go on, wait until venc/npu is reset completely.
Error log:
DDR Version V1.06 20220509 OTP null ff47 F DDRConf1 DDR2, BW=16 Col=10 Bk=4 CS0 Row=13 CS=1 Die BW=16 Size=64MB 528MHz DDR bin out
U-Boot SPL board init U-Boot SPL 2017.09-g8d3df2fd94-220527-dirty #cl (May 27 2022 - 16:54:37)
Change-Id: I0e5c9c4a9f53f53c5b1796ce3f367f785db94709 Signed-off-by: Liang Chen <cl@rock-chips.com>
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