| c571b46d | 28-Dec-2020 |
Jianqun Xu <jay.xu@rock-chips.com> |
ARM: rockchip: rk1808 set gpio0_C2 to pull down
It's a long story to explain why to set gpio0_c2 to pull down, start
from ...
The rk1808 suspend supports to swith 32k clock source, BUT need the
low
ARM: rockchip: rk1808 set gpio0_C2 to pull down
It's a long story to explain why to set gpio0_c2 to pull down, start
from ...
The rk1808 suspend supports to swith 32k clock source, BUT need the
low level for each source clock.
clk_32k --- ext_32k from pmic for example (pin on SoC is AWK13)
|
--- int_32k divided from 24MHz
The pin AWK13 default to be GPIO0_C2 which is normal state defaultly.
When the software try to switch clk_32k from int_32k to ext_32k, but
the pin is in normal state, unluckly for some board it's high level,
the result is the switch never be done, till device try to do suspend
and into a halt state.
Make the gpio0_c2 to be pull down as default state for kernel.
Change-Id: I6ae5859352d9a680166b4c711e25491a60442209
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
show more ...
|
| 45a3782a | 06-Aug-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
rockchip: clk: rk1808: add clk driver for rk1808
Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.
Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9
rockchip: clk: rk1808: add clk driver for rk1808
Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.
Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
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