| c0493076 | 05-Aug-2016 |
Stephen Warren <swarren@nvidia.com> |
mmc: tegra: port to standard clock/reset APIs
Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs
still use custom APIs. Enhance the Tegra MMC driver so that it can operate
wit
mmc: tegra: port to standard clock/reset APIs
Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs
still use custom APIs. Enhance the Tegra MMC driver so that it can operate
with either set of APIs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 73dd5c4c | 08-Aug-2016 |
Stephen Warren <swarren@nvidia.com> |
misc: add Tegra BPMP driver
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such
misc: add Tegra BPMP driver
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 2863a9bf | 06-Aug-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-rockchip |
| b0b3c865 | 29-Jul-2016 |
Kever Yang <kever.yang@rock-chips.com> |
rk3399: add basic soc driver
This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver
Signed-off-by: Kever Yang <kever.yang@rock-ch
rk3399: add basic soc driver
This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| bb6b142f | 25-Jul-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: move CONFIG_PHYS_64BIT to Kconfig
We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so
that it is always available to the build system. Otherwise we can run
into cases wh
treewide: move CONFIG_PHYS_64BIT to Kconfig
We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so
that it is always available to the build system. Otherwise we can run
into cases where we have inconsistent sizes of certain attributes.
Ravi Babu reported offset mismatch of struct dwc3 across files since
commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t").
Since the commit, resource_addr_t points to phys_addr_t, whose size
is dependent on CONFIG_PHYS_64BIT for ARM architecture.
I tried my best to use "select" where possible (for example, ARMv8
architecture) because I think this kind of option is generally user-
unconfigurable. However, I see some of PowerPC boards have 36BIT
defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the
defconfigs for such boards.
CONFIG_36BIT is no longer referenced, so all of the defines were
removed from CONFIG_SYS_EXTRA_OPTIONS.
Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Ravi Babu <ravibabu@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| a78cd861 | 01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions
As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases i
ARM: Rework and correct barrier definitions
As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions. This was causing a failure to
boot of the Linux kernel.
In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions. This however introduces another complexity. Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it. Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier. The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Sandy Patterson <apatterson@sightlogix.com>
Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reported-by: Sandy Patterson <apatterson@sightlogix.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
show more ...
|
| 2c774165 | 29-Jul-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
arm/PSCI: Fixed the backward compatiblity issue
Appended the compatible strings of old version PSCI to the latest
version supported. And there are some psci functions' property must
be added to DT o
arm/PSCI: Fixed the backward compatiblity issue
Appended the compatible strings of old version PSCI to the latest
version supported. And there are some psci functions' property must
be added to DT only for psci version 0.1, including cpu_on, cpu_off,
cpu_suspend, migrate.
Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| 9c7a0a60 | 26-Jul-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq |
| 3288628a | 21-Jul-2016 |
Hongbo Zhang <hongbo.zhang@nxp.com> |
ARMv7: PSCI: ls102xa: move secure text section into OCRAM
LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.
Signed-off-by: Wang Dong
ARMv7: PSCI: ls102xa: move secure text section into OCRAM
LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| aeb901f2 | 21-Jul-2016 |
Hongbo Zhang <hongbo.zhang@nxp.com> |
ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.
Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| 7e742c27 | 21-Jul-2016 |
Hongbo Zhang <hongbo.zhang@nxp.com> |
ARMv7: PSCI: ls102xa: check target CPU ID before further operations
The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do
ARMv7: PSCI: ls102xa: check target CPU ID before further operations
The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| 116339d4 | 21-Jul-2016 |
Hongbo Zhang <hongbo.zhang@nxp.com> |
ARMv7: PSCI: add PSCI v1.0 functions skeleton
This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common frame
ARMv7: PSCI: add PSCI v1.0 functions skeleton
This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| b528b937 | 05-Jul-2016 |
Mingkai Hu <mingkai.hu@nxp.com> |
armv8: fsl_lsch2: Add LS1046A SoC support
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqian
armv8: fsl_lsch2: Add LS1046A SoC support
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| da4d620c | 05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will
armv8: fsl_lsch2: Add SerDes 2 support
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| 86336e60 | 05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl-layerscape: Consolidate the LSCH2 common defines
Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
re
armv8: fsl-layerscape: Consolidate the LSCH2 common defines
Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
readability.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| 79119a4d | 05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <alison.wang@nxp
armv8: fsl-layerscape: Add A72 core detection
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| 69d4b48c | 14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable SD as a source for bootscript
Add support for reading bootscript and bootscript header from SD. Also
renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and
NOR fla
SECURE_BOOT: Enable SD as a source for bootscript
Add support for reading bootscript and bootscript header from SD. Also
renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and
NOR flash.
Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| 028ac8c7 | 14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable chain of trust in SPL framework
Override jump_to_image_no_args function to include validation of
u-boot image using spl_validate_uboot before jumping to u-boot image.
Also define
SECURE_BOOT: Enable chain of trust in SPL framework
Override jump_to_image_no_args function to include validation of
u-boot image using spl_validate_uboot before jumping to u-boot image.
Also define macros in SPL framework to enable crypto operations.
Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| 9729dc95 | 07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping
Remove Soc specific defines and use generic chasis specific defines
for USB controller base address mapping.
Signed-off-by: Rajesh Bhagat <r
include: usb: Rename USB controller base address mapping
Remove Soc specific defines and use generic chasis specific defines
for USB controller base address mapping.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
show more ...
|
| c3c9fd31 | 26-Jul-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-i2c |
| 7fb825f5 | 18-Jul-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
omap5/dra7: i2c: correct register offset for sync register
The register offset of i2c_sysc offset is not correct as per
omap5[1]/dra7[2] TRM, correct the offsets as per the
documentation.
[1] - htt
omap5/dra7: i2c: correct register offset for sync register
The register offset of i2c_sysc offset is not correct as per
omap5[1]/dra7[2] TRM, correct the offsets as per the
documentation.
[1] - http://www.ti.com/lit/pdf/swpu249
[2] - http://www.ti.com/lit/pdf/spruhz6
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
show more ...
|
| 3465f807 | 18-Jul-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
omap4: i2c: correct register offset for sync register
The register offset of i2c_sysc offset is not correct as per
omap4 TRM [1], correct the offsets as per the documentation.
[1] - http://www.ti.c
omap4: i2c: correct register offset for sync register
The register offset of i2c_sysc offset is not correct as per
omap4 TRM [1], correct the offsets as per the documentation.
[1] - http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
show more ...
|
| a617c5d3 | 17-Jul-2016 |
Simon Glass <sjg@chromium.org> |
rockchip: Add a way to obtain the main clock device
On Rockchip SoCs we typically have a main clock device that uses the Soc
clock driver. There is also a fixed clock for the oscillator. Add a funct
rockchip: Add a way to obtain the main clock device
On Rockchip SoCs we typically have a main clock device that uses the Soc
clock driver. There is also a fixed clock for the oscillator. Add a function
to obtain the core clock.
Signed-off-by: Simon Glass <sjg@chromium.org>
show more ...
|
| b339b5db | 15-Jul-2016 |
Heiko Stübner <heiko@sntech.de> |
cosmetic: rockchip: rk3288: rename rkclk_configure_cpu
The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru
cosmetic: rockchip: rk3288: rename rkclk_configure_cpu
The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 8df375b4 | 15-Jun-2016 |
Boris Brezillon <boris.brezillon@free-electrons.com> |
sunxi: Add missing macros to configure the NAND controller clk
We need some macros to manipulate the NAND controller clock.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked
sunxi: Add missing macros to configure the NAND controller clk
We need some macros to manipulate the NAND controller clock.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
show more ...
|