ARM: OMAP4+: Move external phy initialisations to arch specific place.

The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy struct

ARM: OMAP4+: Move external phy initialisations to arch specific place.

The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy structures
for those Socs which do not have a external phy. So by having a weak
function in emif-common and overriding it in OMAP5, avoids the use
of dummy structures.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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omap: am33xx: accomodate input clocks other than 24 Mhz

The PLL setup values currently assume a 24 Mhz input clock.

This patch uses V_OSCK from the board config file to support boards
with differen

omap: am33xx: accomodate input clocks other than 24 Mhz

The PLL setup values currently assume a 24 Mhz input clock.

This patch uses V_OSCK from the board config file to support boards
with different input clock rates.

Signed-off-by: Steve Sakoman <steve@sakoman.com>

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OMAP4+: Force DDR in self-refresh after warm reset

Errata ID:i727

Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequen

OMAP4+: Force DDR in self-refresh after warm reset

Errata ID:i727

Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.

Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.

This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>

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ARM: OMAP3+: Detect reset type

Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.

This will be used to s

ARM: OMAP3+: Detect reset type

Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.

This will be used to skip the module configurations
that are retained across a warm reset.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>

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arm/kirkwood: protect the ENV_SPI #defines

So that they can be redefined by some boards specific values.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Bru

arm/kirkwood: protect the ENV_SPI #defines

So that they can be redefined by some boards specific values.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>

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kw_spi: support spi_claim/release_bus functions

These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuratio

kw_spi: support spi_claim/release_bus functions

These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuration when the access is over.

Since the used pins for the SPI controller can differ (2 possibilities
for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>

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kirkwood: add save functionality kirkwood_mpp_conf function

If a second non NULL argument is given to the kirkwood_mpp_conf
function, it will be used to store the current configuration of the MPP
re

kirkwood: add save functionality kirkwood_mpp_conf function

If a second non NULL argument is given to the kirkwood_mpp_conf
function, it will be used to store the current configuration of the MPP
registers. mpp_save must be a preallocated table of the same size as
mpp_list and it must be zero terminated as well.

A later call to kirkwood_mpp_conf function with this saved list as first
(mpp_conf) argment will set the configuration back.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>

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ATMEL/PIO: Enable new feature of PIO on Atmel device

Enable new PIO feature supported by Atmel SoC.
Using CPU_HAS_PIO3 micro to enable PIO new feature.

Signed-off-by: Bo Shen <voice.shen@atmel.com>

ATMEL/PIO: Enable new feature of PIO on Atmel device

Enable new PIO feature supported by Atmel SoC.
Using CPU_HAS_PIO3 micro to enable PIO new feature.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

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MX28: Fix a typo in mx28_reg_8 macro

The macro mistakenly referred to 32bit struct instead of 8bit one.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@fre

MX28: Fix a typo in mx28_reg_8 macro

The macro mistakenly referred to 32bit struct instead of 8bit one.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>

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i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly

If one PAD does not have mux or pad config register, we need
set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct

Signed-off-by: Jason Liu

i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly

If one PAD does not have mux or pad config register, we need
set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct

Signed-off-by: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

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EXYNOS5: PINMUX: Added default pinumx settings

This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.

Signed-off-by:

EXYNOS5: PINMUX: Added default pinumx settings

This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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Exynos: fix cpuinfo and cpu detecting

Since Exynos architecture have new SoCs,
need to fix cpuinfo correctly.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmi

Exynos: fix cpuinfo and cpu detecting

Since Exynos architecture have new SoCs,
need to fix cpuinfo correctly.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Chander Kashyap <chander.kashyap@linaro.org>

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ARM: OMAP4: Correct the lpddr2 io settings register value.

To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
a

ARM: OMAP4: Correct the lpddr2 io settings register value.

To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.

Correcting the above settings here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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OMAP5: Change voltages for omap5432

Change voltages for OMAP5432

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

OMAP5: DPLL core lock for OMAP5432

No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

OMAP5: EMIF: Add support for DDR3 device

In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done a

OMAP5: EMIF: Add support for DDR3 device

In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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OMAP5: ADD precalculated timings for ddr3

Adding precalculated timings for ddr3 with 1cs
adding required registers for ddr3

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

OMAP5: Configure the io settings for omap5432 uevm board

This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

OMAP5: ADD chip detection for OMAP5432 SOC

This patch adds chip detection for OMAP5432

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

OMAP5: Adding correct Control id code for OMAP5430

Control id code for omap5430 ES1.0 is hard coded with a wrong value.
This patch corrects the value

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

am33xx: Fix i2c sampling rate typo

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>

am33xx: Fill in more cm_wkuppll / cm_perpll

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>

am335x: Correct i2c sysc offset

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>

ARM: OMAP5: Correct the DRAM_ADDR_SPACE_END macro.

OMAP5 evm board has 2GB of memory. So correct the
macro to take in to account of the full dram size.

Signed-off-by: R Sricharan <r.sricharan@ti.co

ARM: OMAP5: Correct the DRAM_ADDR_SPACE_END macro.

OMAP5 evm board has 2GB of memory. So correct the
macro to take in to account of the full dram size.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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am33xx: Do not call init_timer twice

We do not need to call init_timer both in SPL and U-Boot itself, just
SPL needs to initialize the timer.

Signed-off-by: Tom Rini <trini@ti.com>