snowball: Adding architecture dependent initialisation

Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John R

snowball: Adding architecture dependent initialisation

Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

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u8500: Moving prcmu to cpu directory

This is to allow the prcmu functions to be used by multiple
u8500-based processors.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: J

u8500: Moving prcmu to cpu directory

This is to allow the prcmu functions to be used by multiple
u8500-based processors.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

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snowball: Add support for ux500 based snowball board

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Acked-by: Tom Rini <trini@ti.com>
A

snowball: Add support for ux500 based snowball board

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Conflicts:

drivers/gpio/Makefile

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am33xx evm: Update secure_emif_sdram_config during ddr init

This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume

am33xx evm: Update secure_emif_sdram_config during ddr init

This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.

Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>

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da8xx/hawkboard: Add support for ohci host controller

Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.

da8xx/hawkboard: Add support for ohci host controller

Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.

Move the usb header for da8xx platforms under arch-davinci.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>

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omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms

Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all arm

omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms

Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms. As part of this we change some of the macros that are used
to be more clear. Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we
should have been doing this initially and do now.

Cc: Sricharan R <r.sricharan@ti.com>
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Correct MMC1, remove MMC2 support

- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value

Signed-off-by: Tom Rini <trini@ti.

am33xx: Correct MMC1, remove MMC2 support

- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value

Signed-off-by: Tom Rini <trini@ti.com>

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mxs: Reowork SPL to use 'mxs' prefix for methods

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

mxs: prefix register structs with 'mxs' prefix

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

mxs: prefix register acessor macros with 'mxs' prefix

As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.

Signed-off-by: Otavio Salvador <ot

mxs: prefix register acessor macros with 'mxs' prefix

As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

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mxs: reorganize source directory for easy sharing of code in i.MXS SoCs

Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to

mxs: reorganize source directory for easy sharing of code in i.MXS SoCs

Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>

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MX28: extend print_cpuinfo() to use chip information

The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.

Signed-off-by: Otavio Sal

MX28: extend print_cpuinfo() to use chip information

The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

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arm : Atmel : add at91sam9x5ek board support

Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35

Using at91sam9x5

arm : Atmel : add at91sam9x5ek board support

Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35

Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

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DaVinci DA8xx: replace magic number for DDR speed

Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which do

DaVinci DA8xx: replace magic number for DDR speed

Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>

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DaVinci DA850: UART2 clock ID comes from ASYNC3

On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
contro

DaVinci DA850: UART2 clock ID comes from ASYNC3

On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>

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DaVinci DA8xx: tidy up clock ID definition

Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbe

DaVinci DA8xx: tidy up clock ID definition

Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Rework pinmux functions

- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
- Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create

am33xx: Rework pinmux functions

- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
- Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.

Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Add support for TI AM335x StarterKit EVM

- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
config_ddr with.
- Both of the

am33xx: Add support for TI AM335x StarterKit EVM

- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
config_ddr with.
- Both of the above require filling in the header structure early, move
it into the data section.

Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support

Signed-off-by: Tom Rini <trini@ti.com>

am33xx: Correct and clean up ddr_regs struct

The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in

am33xx: Correct and clean up ddr_regs struct

The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.

Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Do not touch 'ratio1' fields

The various ratio1 fields are not documented in any of the documentation
I can find. Removing these and testing has yielded success, so remove
the code that set

am33xx: Do not touch 'ratio1' fields

The various ratio1 fields are not documented in any of the documentation
I can find. Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.

Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Rework config_io_ctrl slightly

This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation

am33xx: Rework config_io_ctrl slightly

This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation). Rather than defining a struct and setting the
value repeatedly, just pass in the value.

Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Use emif_regs struct for storing initialization values

Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.

Signed-off

am33xx: Use emif_regs struct for storing initialization values

Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.

Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Turn a number of 'int' functions to 'void'

A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
tu

am33xx: Turn a number of 'int' functions to 'void'

A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.

Signed-off-by: Tom Rini <trini@ti.com>

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am33xx: Document what we're doing with ddrctrl->ddrckectrl

- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
w

am33xx: Document what we're doing with ddrctrl->ddrckectrl

- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
we're operating in the normal mode where EMIF/PHY clock is controlled
by the PHY.

Signed-off-by: Tom Rini <trini@ti.com>

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