rockchip: atags: follow miniloader bootdev type definitions

Change-Id: Id9fbb25aadc4dafe0432b38e27b219d9dfa5108f
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

clk: rockchip: rk3288: fix up the dclk_vop freq setting

Change-Id: I960a02cba63076afbc845e5ccdfb9f85a553d38b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk312x: add cpll freq init

Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop displ

clk: rockchip: rk312x: add cpll freq init

Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop display, the cpll need to set init freq for other
children clk.

Change-Id: Ia45892dd3c8efb77cf32b631329d927aceb8dd86
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: atags: add tag_atf_mem support

it's mainly for U-Boot to reserve ATF memory region.

Change-Id: I1039204c263adf91e84ec3b813094e4cf588013f
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

rockchip: atags: add serial id

Change-Id: I13342303a3103b3610eec932b014f9e99e148381
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

clk: rockchip: rk1808: fix up the dclk_raw/lite set rate error

Change-Id: I0b8c7d0e15501c7ecc3c5acb0e0844e722ad18ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk1808: support pclk_pmu freq setting

set pclk_pmu freq before ppll freq setting.

Change-Id: Ieab142dd9e41d98d9798be08a0f01f941d3ad9a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chi

clk: rockchip: rk1808: support pclk_pmu freq setting

set pclk_pmu freq before ppll freq setting.

Change-Id: Ieab142dd9e41d98d9798be08a0f01f941d3ad9a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: move BROM_BOOTSOURCE_ID_ADDR to bootrom.h

The macro BROM_BOOTSOURCE_ID_ADDR does not belong to sdram_common.h

Change-Id: I0490ff10b08287d71e3231baa999d3f096068c7c
Signed-off-by: Kever Yan

rockchip: move BROM_BOOTSOURCE_ID_ADDR to bootrom.h

The macro BROM_BOOTSOURCE_ID_ADDR does not belong to sdram_common.h

Change-Id: I0490ff10b08287d71e3231baa999d3f096068c7c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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clk: rockchip: px30: add support clock for SCLK_I2S1

Change-Id: Iaaacd6fdabe2c702202ffe09dc95cd6d648597d6
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

rockchip: rk_atags: add memset/memcpy for TINY TPL

For some TPL with TINY mode didn't define LIBGENERIC_SUPPORT,
need to realize memset/memcpy for rk_atags whit TPL.

Change-Id: I9c7a343836592aa03fc

rockchip: rk_atags: add memset/memcpy for TINY TPL

For some TPL with TINY mode didn't define LIBGENERIC_SUPPORT,
need to realize memset/memcpy for rk_atags whit TPL.

Change-Id: I9c7a343836592aa03fcee910404fb2f1e37a4989
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

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rockchip: atags: add atags_stat()

Change-Id: I3ab086747cb9232118fd4e4f131648c242574309
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

rockchip: atags: add ram partition support

Maybe there is no flash storage for some SoC which is used
as coprocessor, preloader will load images for U-Boot and
pass partition info by atags.

Change-

rockchip: atags: add ram partition support

Maybe there is no flash storage for some SoC which is used
as coprocessor, preloader will load images for U-Boot and
pass partition info by atags.

Change-Id: Ieb6efff80cb615b3b5a7bcd51c672649f3c97115
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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rockchip: atags: add atags_is_available()

we would compatible pre-loaders parameters deliver by atags
and fixed memory address(legacy), this interface gives a way
to detect if atags is used now.

Ch

rockchip: atags: add atags_is_available()

we would compatible pre-loaders parameters deliver by atags
and fixed memory address(legacy), this interface gives a way
to detect if atags is used now.

Change-Id: I75c96faa23812c621e4084c58398605df29d043d
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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rockchip: ARM: tpl: add TPL_TINY_FRAMEWORK flow for arm

If sram size is small for TPL build, it can defined
CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size.
For ARM if defined CONFIG_TPL_TINY_FRAMEWORK

rockchip: ARM: tpl: add TPL_TINY_FRAMEWORK flow for arm

If sram size is small for TPL build, it can defined
CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size.
For ARM if defined CONFIG_TPL_TINY_FRAMEWORK when build TPL, after
save_boot_params(), it jump to board_init_f() directly, then return to
maskrom. and stack also use maskrom defined result, never change the SP.

Change-Id: I9a90d031a5d200f86c437175e9ea47e8a34062ac
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

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rockchip: add rk atags support

The atags information is deliverd among rockchip pre-loaders,
i.e. ddr, miniloader, atf, tos and U-boot, etc.

Notice: the first pre-loader who creates the atags must

rockchip: add rk atags support

The atags information is deliverd among rockchip pre-loaders,
i.e. ddr, miniloader, atf, tos and U-boot, etc.

Notice: the first pre-loader who creates the atags must call
atags_destroy() before atags_set_tag(), because atags_set_tag()
may detect last valid and existence ATAG_CORE tag in memory and
lead a wrong setup, that is not what we expect.

Change-Id: I6c2bf7633699af14afd472f2069e7d3ed91f5196
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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rockchip: clk: rk1808: add clk driver for rk1808

Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.

Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9

rockchip: clk: rk1808: add clk driver for rk1808

Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.

Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: rk1808: add soc basic support

RK3308 is a Soc from Rockchip, which embedded with dual
ARM Cortex-A35.

Change-Id: Ieda5705a058ef6a7be1966ccfff62eea66ca45db
Signed-off-by: Joseph Chen <chen

rockchip: rk1808: add soc basic support

RK3308 is a Soc from Rockchip, which embedded with dual
ARM Cortex-A35.

Change-Id: Ieda5705a058ef6a7be1966ccfff62eea66ca45db
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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clk: rockchip: rk3399: Improve the aclk_perilp0 frequency

Set aclk_perilp0 to 300M,
To improve the performance of dual USB transmission.

Change-Id: I3842742e87ed1d483215ec7bccb75b1c0ed503bf
Signed-

clk: rockchip: rk3399: Improve the aclk_perilp0 frequency

Set aclk_perilp0 to 300M,
To improve the performance of dual USB transmission.

Change-Id: I3842742e87ed1d483215ec7bccb75b1c0ed503bf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: px30: Add support to initialize npll rate

Change-Id: If98ed54ad785a40efae7da78c5f0122158a3de61
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: vendor: Completing the vendor part planning for flash

1.Nand flash and SPI Nand large capacity case;
|64KB vendor part 1| p2 | storage ....|
2.Spi nor small capacity case;
|8KB offset|

rockchip: vendor: Completing the vendor part planning for flash

1.Nand flash and SPI Nand large capacity case;
|64KB vendor part 1| p2 | storage ....|
2.Spi nor small capacity case;
|8KB offset|4KB vendor part 1| p2 | p3 | p4| storage ...|
3.Support vendor ops register.

Change-Id: Ifbf5f3499b0976202e9df63936a06d8fcdd68aa4
Signed-off-by: Dingqiang Lin <jon.lin@rock-chips.com>

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rockchip: vendor: export vendor_item structure

Export vendor_item structure into head file that other
moudules may quote directly.

Change-Id: If791f5da8ac45f46f872a8f872af9bf9e2365a37
Signed-off-by

rockchip: vendor: export vendor_item structure

Export vendor_item structure into head file that other
moudules may quote directly.

Change-Id: If791f5da8ac45f46f872a8f872af9bf9e2365a37
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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rockchip: clk: rk3308: Add support to set and get armclk rate

Change-Id: I2f4bbed7d6c43f340892968ce8e2ed417f975e97
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: rk3308: Use common apis for setting and getting pll rate

Change-Id: Id60ebe239148c7fa7bb8ca1abb411570596c6e28
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Add support to get vopl aclk and dclk

Change-Id: Id40cbddf780889e308839b7beb2cfb894d407914
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Add px30_clk_init()

Add support to initialize gpll, bus and peri clock rate.

Change-Id: I84f496094606ac2231ea27ad9072b079c45f9f94
Signed-off-by: Finley Xiao <finley.xiao@rock-c

rockchip: clk: px30: Add px30_clk_init()

Add support to initialize gpll, bus and peri clock rate.

Change-Id: I84f496094606ac2231ea27ad9072b079c45f9f94
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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