| 828bd14c | 19-Feb-2013 |
Eric Nelson <eric.nelson@boundarydevices.com> |
i.MX6DL: define IOMUX pads NANDF_CS1-3 for use as GPIO
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> |
| 714afa64 | 19-Feb-2013 |
Eric Nelson <eric.nelson@boundarydevices.com> |
i.MX6: crm_regs: define IOMUXC_GPR4/6/7
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> |
| 4f60c49a | 19-Feb-2013 |
Eric Nelson <eric.nelson@boundarydevices.com> |
i.MX6: crm_regs: define CCM_CCGRx for use in board config files
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> |
| cfb8b9d3 | 19-Feb-2013 |
Eric Nelson <eric.nelson@boundarydevices.com> |
i.MX6: consolidate pad names for multi-CPU boards
Rename all i.MX6 pad declarations to MX6_PAD_x, so a board
may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo
(MX6DL) by including the
i.MX6: consolidate pad names for multi-CPU boards
Rename all i.MX6 pad declarations to MX6_PAD_x, so a board
may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo
(MX6DL) by including the proper header.
Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd
only support MX6Q, so they include mx6q_pins.h.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
show more ...
|
| 9cd9b34d | 23-Feb-2013 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm |
| a5627914 | 21-Feb-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' |
| 03268374 | 21-Feb-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'
This pulls the three following ZYNQ commits into ARM master:
7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board
59c651f
Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'
This pulls the three following ZYNQ commits into ARM master:
7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board
59c651f4: arm: zynq: Add SLCR support with system reset
00ed3458: arm: zynq: Add lowlevel initialization to C
show more ...
|
| 03414ac4 | 07-Feb-2013 |
Holger Hans Peter Freyther <holger@freyther.de> |
gpio: Build the da8xx_gpio code for the davinci644x device
The differences include the number of GPIOs and that one is
not required to set the pinmux on request.
Signed-off-by: Holger Hans Peter Fr
gpio: Build the da8xx_gpio code for the davinci644x device
The differences include the number of GPIOs and that one is
not required to set the pinmux on request.
Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
show more ...
|
| 51ff1eda | 12-Feb-2013 |
Rajeshwari Shinde <rajeshwari.s@samsung.com> |
EXYNOS5: Add function to setup set ps hold
This patch adds a function to set ps_hold data driving value high.
This enables the machine to stay powered on even after the initial
power-on condition go
EXYNOS5: Add function to setup set ps hold
This patch adds a function to set ps_hold data driving value high.
This enables the machine to stay powered on even after the initial
power-on condition goes away(e.g. power button).
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
show more ...
|
| da07c21b | 05-Feb-2013 |
Ilya Yanok <ilya.yanok@cogentembedded.com> |
am33xx: support for booting via usbeth
This patch adds BOOT_DEVICE define for USB booting and fixes
spl_board_init function to call arch_misc_init (this is the place there
musb is initialized).
Sig
am33xx: support for booting via usbeth
This patch adds BOOT_DEVICE define for USB booting and fixes
spl_board_init function to call arch_misc_init (this is the place there
musb is initialized).
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
show more ...
|
| b9f56698 | 01-Feb-2013 |
Tomas Novotny <tomas@novotny.cz> |
da8xx: Add the missing pinmux for da830 to the gpio driver
The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of
kernel version 3.7.5. If the driver is used for the da850, then SoC
da8xx: Add the missing pinmux for da830 to the gpio driver
The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of
kernel version 3.7.5. If the driver is used for the da850, then SoC
variant must be specified by CONFIG_SOC_DA850.
Signed-off-by: Tomas Novotny <tomas@novotny.cz>
Cc: Tom Rini <trini@ti.com>
show more ...
|
| 951c6baa | 12-Feb-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arm |
| 76c91e66 | 07-Feb-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.
Comparing the watchdog behaviour o
mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.
Comparing the watchdog behaviour on a revB versus revC board:
- On a mx6qsabresd revB:
U-Boot > reset
resetting ...
U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
CPU: Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...
- On a mx6qsabresd revC:
U-Boot > reset
resetting ...
U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
CPU: Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR
So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.
Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
show more ...
|
| 2fc65e28 | 28-Jan-2013 |
Tom Warren <twarren.nvidia@gmail.com> |
Tegra114: Add arch-tegra114 include files
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in
Tegra114: Add arch-tegra114 include files
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
show more ...
|
| b19f5749 | 29-Jan-2013 |
Allen Martin <amartin@nvidia.com> |
tegra: add SPI SLINK driver
Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a gener
tegra: add SPI SLINK driver
Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 91673e2a | 29-Jan-2013 |
Allen Martin <amartin@nvidia.com> |
tegra: add addresses of SPI SLINK controllers
Add I/O addresses of SPI SLINK controllers 1-6
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by:
tegra: add addresses of SPI SLINK controllers
Add I/O addresses of SPI SLINK controllers 1-6
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 4727a13b | 22-Jan-2013 |
Stephen Warren <swarren@nvidia.com> |
tegra: rename FUNCMUX_UART2_UARTB
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.
Signed-off-by: Stephen Warren <swarre
tegra: rename FUNCMUX_UART2_UARTB
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| f29f086a | 23-Jan-2013 |
Tom Warren <twarren@nvidia.com> |
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c
Some T30
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c
Some T30 tables needed whitespace fixes due to checkpatch complaints.
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| d83152d8 | 18-Jan-2013 |
Tom Warren <twarren@nvidia.com> |
Tegra: T20: Remove unused 'SLOW' SoC ID and PLLX table entry
Signed-off-by: Tom Warren <twarren@nvidia.com> |
| 13526f71 | 14-Jan-2013 |
Jeff Lance <jefflance01@gmail.com> |
Add DDR3 support for AM335x-EVM (Version 1.5A)
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.
[Hebbar Gururaja <gururaja.hebbar@ti.com>]
- Resolve merge conflict
Add DDR3 support for AM335x-EVM (Version 1.5A)
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.
[Hebbar Gururaja <gururaja.hebbar@ti.com>]
- Resolve merge conflict while rebasing. File structure is
changed in the mainline. So re-arrange the code accordingly.
- Update commit message to reflect the DDR3 part number
Signed-off-by: Jeff Lance <j-lance1@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
show more ...
|
| 1c1b7c37 | 11-Jan-2013 |
Lars Poeschel <poeschel@lemonage.de> |
pcm051: Add support for Phytec phyCORE-AM335x
The board is named pcm051 and has this hardware:
SOC: TI AM3359
DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB
ETH 1: LAN8710AI
SPI-Flash: W25Q64BVSSIG
RTC: R
pcm051: Add support for Phytec phyCORE-AM335x
The board is named pcm051 and has this hardware:
SOC: TI AM3359
DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB
ETH 1: LAN8710AI
SPI-Flash: W25Q64BVSSIG
RTC: RV-4162-C7
I2C-EEPROM: CAT32WC32
NAND: MT29F4G08_VFPGA63
PMIC: TPS65910A3
LCD
Supported:
UART 1
MMC/SD
ETH 1
USB
I2C
SPI
Not yet supported:
NAND
RTC
LCD
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
[trini: Add #define CONFIG_PHY_ADDR 0 to config]
Signed-off-by: Tom Rini <trini@ti.com>
show more ...
|
| aca0b8b4 | 11-Jan-2013 |
Lars Poeschel <poeschel@lemonage.de> |
am33xx: add a pulldown macro to pinmux config
Signed-off-by: Lars Poeschel <poeschel@lemonage.de> |
| 00ed3458 | 04-Feb-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Add lowlevel initialization to C
Do lowlevel initialization directly in C. Zynq do not
require to do it in asm.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
| 59c651f4 | 04-Feb-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Add SLCR support with system reset
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board
arm: zynq: Add SLCR support with system reset
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|
| baa1e536 | 13-Dec-2012 |
Simon Glass <sjg@chromium.org> |
arm: Use generic global_data
Signed-off-by: Simon Glass <sjg@chromium.org> |