| 3e976357 | 26-Dec-2013 |
Rajeshwari Birje <rajeshwari.s@samsung.com> |
EXYNOS5420: Add power register structure.
Add structure for power register for Exynos5420
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Sign
EXYNOS5420: Add power register structure.
Add structure for power register for Exynos5420
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| e69847ab | 26-Dec-2013 |
Rajeshwari Birje <rajeshwari.s@samsung.com> |
Exynos5420: Add base addresses for 5420
Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Aksh
Exynos5420: Add base addresses for 5420
Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| 71ebb335 | 26-Dec-2013 |
Rajeshwari Birje <rajeshwari.s@samsung.com> |
EXYNOS5: Create a common board file
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform specific code.
Signe
EXYNOS5: Create a common board file
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| b5e01eec | 10-Dec-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enab
ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| d3daba10 | 10-Dec-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief descr
ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| cf04d032 | 10-Dec-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is lock
ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE VDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz
Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| 4892495e | 10-Dec-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: mux: Update mux data
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
| 1fb68b84 | 10-Dec-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Update Current Booting devices list
Current Booting devices list is different from that of AM33xx.
Updating the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
| 9f1a8cd3 | 10-Dec-2013 |
Sekhar Nori <nsekhar@ti.com> |
ARM: AM43XX: board: add support for reading onboard EEPROM
Add support for reading onboard EEPROM to enable
board detection.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla
ARM: AM43XX: board: add support for reading onboard EEPROM
Add support for reading onboard EEPROM to enable
board detection.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| 369cbe1e | 10-Dec-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Adapt to ti_armv7_common.h config file
Use ti_armv7_common.h config file to inclde the common
configs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
| 7ca1b2a2 | 10-Dec-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: AM43xx: Update the base addresses of modules
PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
| 766afc3d | 20-Nov-2013 |
Alban Bedel <alban.bedel@avionic-design.de> |
arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the reg
arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swrren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 3346cbb8 | 13-Nov-2013 |
Alban Bedel <alban.bedel@avionic-design.de> |
ARM: tegra: support SKU b1 of Tegra30
Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Julian Scheel <julian.sch
ARM: tegra: support SKU b1 of Tegra30
Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 164d9846 | 28-Nov-2013 |
Giuseppe Pagano <giuseppe.pagano@seco.com> |
nitrogen6x: Move setup_sata to common part
Move setup_sata function definition from platform file nitrogen6x.c
to arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagan
nitrogen6x: Move setup_sata to common part
Move setup_sata function definition from platform file nitrogen6x.c
to arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Eric Nelson <eric.nelson@boundarydevices.com>
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| b47abc36 | 13-Nov-2013 |
Eric Nelson <eric.nelson@boundarydevices.com> |
i.MX6 (DQ/DLS): use macros for mux and pad declarations
This allows the use of either or both declarations from
the files mx6q_pins.h and mx6dl_pins.h.
All board files should include <asm/arch/mx6-
i.MX6 (DQ/DLS): use macros for mux and pad declarations
This allows the use of either or both declarations from
the files mx6q_pins.h and mx6dl_pins.h.
All board files should include <asm/arch/mx6-pins.h>
with one of the following defined in boards.cfg
MX6Q - for boards targeting i.MX6Q or i.MX6D
MX6DL - for boards targeting i.MX6DL
MX6S - for boards targeting i.MX6S
MX6QDL - for boards that support any of the above with
run-time detection
Pad declarations will be MX6_PAD_x for single-variant boards
and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both
processor classes.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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| 052fb196 | 05-Dec-2013 |
Dan Murphy <dmurphy@ti.com> |
arm: am437: Fix offset for USB registers
Fix the offset for the USB clock registers
Signed-off-by: Dan Murphy <dmurphy@ti.com> |
| dcc23576 | 04-Dec-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: OMAP4: Move TEXT_BASE down to non-HS limit
With the current scenario SPL size is being overlapped with the public
stack and not allowing any OMAP4 device to boot. So the suggestion came
up was
ARM: OMAP4: Move TEXT_BASE down to non-HS limit
With the current scenario SPL size is being overlapped with the public
stack and not allowing any OMAP4 device to boot. So the suggestion came
up was to move the TEXT_BASE down to non-HS limit. Fixing the same and
also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image
downloadable area.
Discussion on this can be seen here:
https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html
Tested on OMAP4460 PANDA.
Reported-by: Chao Xu <caesarxuchao@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| f15ea6e1 | 10-Dec-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyard
Needed manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compul
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyard
Needed manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compulab/cm_t335/u-boot.lds
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| 934e3b52 | 29-Nov-2013 |
Andreas Bießmann <andreas.devel@googlemail.com> |
at91: redefine legacy GPIO PIN_BASE
In order to get the very same value for legacy pin definitions and new gpio
definitions set the legacy PIN_BASE to 0.
Signed-off-by: Andreas Bießmann <andreas.de
at91: redefine legacy GPIO PIN_BASE
In order to get the very same value for legacy pin definitions and new gpio
definitions set the legacy PIN_BASE to 0.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
show more ...
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| 9ecc922e | 29-Nov-2013 |
Andreas Bießmann <andreas.devel@googlemail.com> |
at91: add new gpio pin definitions
This patch define new names for GPIO pins on at91 devices. Follow up patches
will convert the whole infrastructure to use these new definitions.
Signed-off-by: An
at91: add new gpio pin definitions
This patch define new names for GPIO pins on at91 devices. Follow up patches
will convert the whole infrastructure to use these new definitions.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Bo Shen <voice.shen@atmel.com>
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| 375a4496 | 06-Dec-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' |
| c35cf8dc | 06-Dec-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' |
| f33b9bd3 | 30-Nov-2013 |
Michael Trimarchi <michael@amarulasolutions.com> |
arm: omap3: Enable clocks for peripherals only if they are used
This patch change the per_clocks_enable() function used in OMAP3
code to enable peripherals clocks. Only required clock should be
acti
arm: omap3: Enable clocks for peripherals only if they are used
This patch change the per_clocks_enable() function used in OMAP3
code to enable peripherals clocks. Only required clock should be
activated. So if the board use the uart(x) as a console we need
to activate it. The Board's config should include define to enable
every subsystem that the board use. For a complete list
of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER
should be checked.
Right now the bootloader can enable and disable clocks for:
uart(x) using CONFIG_SYS_NS16550
gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 }
i2c bus using CONFIG_DRIVER_OMAP34XX_I2C.
Not required gptimer(x) and mcbsp(x) for booting are disabled by default and
are not supported by any define.
Their activation need to included in the per_clocks_enable if the
peripheral is included. Not booting board should enable the peripheral
clock connected to their driver
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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|
| 7988bd4e | 06-Dec-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' |
| 01322004 | 03-Dec-2013 |
Jaehoon Chung <jh80.chung@samsung.com> |
arm: exynos: remove the unused define.
These defines didn't use anywhere.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Minky
arm: exynos: remove the unused define.
These defines didn't use anywhere.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
show more ...
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