Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

ARM: exynos: clock: modify the set_mmc_clk for exynos4

Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using th

ARM: exynos: clock: modify the set_mmc_clk for exynos4

Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

show more ...

Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'

Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

Merge branch 'master' of git://git.denx.de/u-boot-arm

usb: tegra: support device mode

A few changes are made to the Tegra EHCI driver so that it can set
everything up for device-mode operation on the first USB controller.
This can be used in conjunctio

usb: tegra: support device mode

A few changes are made to the Tegra EHCI driver so that it can set
everything up for device-mode operation on the first USB controller.
This can be used in conjunction with ci_udc.c to operate as a USB
device.

Detailed changes are:

* Rename set_host_mode() to set_up_vbus() since that's really what it
does.

* Modify set_up_vbus() to know whether it's initializing in host or
device mode, and:

- Skip the external VBUS check in device mode, since external VBUS is
expected in this case.

- Disable VBUS output in device mode.

* Modify init_phy_mux() to know whether it's initializing in host or
device mode, and hence skip setting USBMODE_CM_HC (which enables host
mode) in device mode. See the comments in that function for why this
is safe w.r.t. the ordering requirements of PHY selection.

* Modify init_utmi_usb_controller() to force "b session valid" in device
mode, since the HW requires this. This is done in UTMI-specific code,
since we only support device mode on the first USB controller, and that
controller can only talk to a UTMI PHY.

* Enhance ehci_hcd_init() to error-check the requested host-/device-mode
vs. the dr_mode (dual-role mode) value present in device tree, and the
HW configurations which support device mode.

* Enhance ehci_hcd_init() not to skip HW initialization when switching
between host and device mode on a controller. This requires remembering
which mode the last initialization used.

Cc: Jim Lin <jilin@nvidia.com>
Cc: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

show more ...

ARM: zynq: ehci: Added USB host driver support

Added USB host driver for zynq.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

ARM: zynq: Add MIO detection code

Add run-time MIO pin detection to get actual
pin configuration for specific periphery.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

ARM: zynq: Fix bootmode mask

Bootmode mask was defined as 0x0F, but documentation mentions 0x07.
Experiments show that bit "3" is the JTAG chain configuration.
Change the mask to "7" to allow system

ARM: zynq: Fix bootmode mask

Bootmode mask was defined as 0x0F, but documentation mentions 0x07.
Experiments show that bit "3" is the JTAG chain configuration.
Change the mask to "7" to allow systems with a different chain
configuration to boot correctly.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

show more ...

ARM: zynq: Added efuse status register base address

Added efuse status register base address. This register
is used for determining whether efuse was blown or not.
Also, added the zynq_get_silicon_v

ARM: zynq: Added efuse status register base address

Added efuse status register base address. This register
is used for determining whether efuse was blown or not.
Also, added the zynq_get_silicon_version() to get the
silicon version of the zynq board.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

show more ...

ARM: OMAP5: add CKO buffer control mask

Add CKOBUFFER_CLK_EN bit mask enabling FREF_XTAL_CLK clock.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>

ARM: OMAP5: add UART4 support

Add UART4 base address.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>

am33xx: add SSC enable macro

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>

ARM: tegra: add function to enable input clamping on tristate

The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a fun

ARM: tegra: add function to enable input clamping on tristate

The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a function to the pinmux driver to allow boards to do this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

show more ...

ARM: tegra: add GPIO initialization table function

The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins,

ARM: tegra: add GPIO initialization table function

The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. Add a feature to the GPIO driver
which executes a GPIO configuration table. Board files will use this to
implement the correct HW initialization procedure.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

show more ...

ARM: tegra: allow pinmux mux option not to be set by init tables

Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shoul

ARM: tegra: allow pinmux mux option not to be set by init tables

Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change
the mux option in HW.

For pins that will be used as GPIOs, the mux option is irrelevant, so we
simply don't want to define any mux option in the pinmux initialization
table.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

show more ...

ARM: tegra: set CONFIG_SYS_MMC_MAX_DEVICE

If CONFIG_API is ever to be enabled on Tegra, this define must be set,
since api/api_storage.c uses it.

A couple of annoyting things about CONFIG_SYS_MMC_M

ARM: tegra: set CONFIG_SYS_MMC_MAX_DEVICE

If CONFIG_API is ever to be enabled on Tegra, this define must be set,
since api/api_storage.c uses it.

A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE

1) It isn't documented in README. The same is true for a lot of similar
defines used by api_storage.c.

2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the
valid values are 0..n-1 not 0..n.

However, I this patch does not address those shortcomings.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

show more ...

S5P: Exynos: Add GPIO pin numbering and rename definitions

This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the b

S5P: Exynos: Add GPIO pin numbering and rename definitions

This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided
into different parts where ever they have holes in them.

* Rename GPIO definitions from GPIO_... to S5P_GPIO_...
These changes were done to enable cmd_gpio for EXYNOS and
cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
getting a error during compilation.

* Adds support for name to gpio conversion in s5p_gpio to enable
gpio command EXYNOS SoCs. Function has been added to asm/gpio.h
to decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00

Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

show more ...

common/board_f: Initialized global data for generic board

Some platforms (tested on mpc85xx, mpc86xx) use global data before calling
function baord_inti_f(). The data should not be cleared later. An

common/board_f: Initialized global data for generic board

Some platforms (tested on mpc85xx, mpc86xx) use global data before calling
function baord_inti_f(). The data should not be cleared later. Any arch
which uses global data in generic board board_init_f() should define
CONFIG_SYS_GENERIC_GLOBAL_DATA.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Simon Glass <sjg@chromium.org>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Simon Glass <sjg@chromium.org>

show more ...

bd_info: remove bi_barudrate member from struct bd_info

gd->bd->bi_baudrate is a copy of gd->baudrate.

Since baudrate is a common feature for all architectures,
keep gd->baudrate only.

It is true

bd_info: remove bi_barudrate member from struct bd_info

gd->bd->bi_baudrate is a copy of gd->baudrate.

Since baudrate is a common feature for all architectures,
keep gd->baudrate only.

It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)

show more ...

imx25: Add new hardware registers

Signed-off-by: Thomas Diener <dietho@gmx.de>

iomux-v3: Add support for mx6sl LVE bit

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL
register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC

iomux-v3: Add support for mx6sl LVE bit

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL
register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the
calculation easier we can define it as a flag in bit 1, since this bit is unused.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Otavio Salvador <otavio@ossystems.com.br>

show more ...

Merge branch 'u-boot/master'

Conflicts:
drivers/net/Makefile

(trivial merge)

usb: ehci: rmobile: Add support ehci host driver of rmobile SoCs

The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.

Signed-off-by: No

usb: ehci: rmobile: Add support ehci host driver of rmobile SoCs

The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Marek Vasut <marex@denx.de>

show more ...