| 2358fc8e | 05-Sep-2014 |
Ajay Kumar <ajaykumar.rs@samsung.com> |
ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by:
ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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|
| 496f0e47 | 05-Sep-2014 |
Ajay Kumar <ajaykumar.rs@samsung.com> |
arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the pa
arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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|
| f0017175 | 05-Sep-2014 |
Ajay Kumar <ajaykumar.rs@samsung.com> |
exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the func
exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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|
| 4fb4d55a | 01-Sep-2014 |
Przemyslaw Marczak <p.marczak@samsung.com> |
arch:exynos: boot mode: add get_boot_mode(), code cleanup
This patch introduces code clean-up for exynos boot mode check.
It includes:
- removal of typedef: boot_mode
- move the boot mode enum to ar
arch:exynos: boot mode: add get_boot_mode(), code cleanup
This patch introduces code clean-up for exynos boot mode check.
It includes:
- removal of typedef: boot_mode
- move the boot mode enum to arch-exynos/power.h
- add bootmode for sequence: eMMC 4.4 ch4 / SD ch2
- add new function: get_boot_mode() for OM[5:1] pin check
- update spl boot code
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Changes v5:
- exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2)
Changes v6:
- none
changes v7:
- change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| e6c9428a | 28-Aug-2014 |
Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> |
keystone2: use readl/writel functions instead of redefinition
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@
keystone2: use readl/writel functions instead of redefinition
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
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|
| ddd960e6 | 30-Aug-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
tegra: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.
Insert the Tegra SoC sele
tegra: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.
Insert the Tegra SoC select menu between the arch select and the
board select.
Architecture select
|-- Tegra Platform (Tegra)
|- Tegra SoC select (Tegra20 / 30 / 114 / 124)
|- Board select
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:
config TEGRA
bool
select SPL
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
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|
| da1f5ac2 | 11-Aug-2014 |
Scott Branden <sbranden@broadcom.com> |
arm: add Cygnus and NSP boards
The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.
Signed-off-by: Scott
arm: add Cygnus and NSP boards
The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
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|
| c4b45009 | 11-Aug-2014 |
Scott Branden <sbranden@broadcom.com> |
arm: iproc: Initial commit of iproc architecture code
The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.
Signed-off-by: Scott Branden <sbranden
arm: iproc: Initial commit of iproc architecture code
The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
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|
| b0e31c7b | 06-Aug-2014 |
Stefan Agner <stefan@agner.ch> |
arm: vf610: add NFC clock support
Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.
Signed-off-by: Stefan Agner <stefan@agner.ch> |
| baa31344 | 06-Aug-2014 |
Stefan Agner <stefan@agner.ch> |
arm: vf610: add NFC pin mux
Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.
Signed-off-by: Stefan
arm: vf610: add NFC pin mux
Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.
Signed-off-by: Stefan Agner <stefan@agner.ch>
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|
| 2d66a0fd | 02-Aug-2014 |
Jiandong Zheng <jdzheng@broadcom.com> |
arm: bcm281xx: Add Ethernet Clock support
Enable Ethernet clock when Broadcom StarFighter2 Ethernet block
(CONFIG_BCM_SF2_ETH) is enabled.
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signe
arm: bcm281xx: Add Ethernet Clock support
Enable Ethernet clock when Broadcom StarFighter2 Ethernet block
(CONFIG_BCM_SF2_ETH) is enabled.
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
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|
| 99b97106 | 14-Jul-2014 |
Pavel Machek <pavel@denx.de> |
socfpga: initialize designware ethernet
Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environme
socfpga: initialize designware ethernet
Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.
Signed-off-by: Pavel Machek <pavel@denx.de>
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|
| 3ab019e1 | 22-Jul-2014 |
Chin Liang See <clsee@altera.com> |
socfpga: Fix SOCFPGA build error for Altera dev kit
To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtua
socfpga: Fix SOCFPGA build error for Altera dev kit
To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtual target. With that, U-Boot
is booting well and SPL still lack of few drivers.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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|
| 51fb455f | 19-Jul-2014 |
Pavel Machek <pavel@denx.de> |
socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.
This fixes structure to match har
socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.
This fixes structure to match hardware.
Signed-off-by: Pavel Machek <pavel@denx.de>
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|
| 8863aa5c | 22-Jun-2014 |
Jeroen Hofstee <jeroen@myspectrum.nl> |
ARM:asm:io.h use static inline
When compiling u-boot with W=1 the extern inline void for
read* is likely causing the most noise. gcc / clang will
warn there is never a actual declaration for these f
ARM:asm:io.h use static inline
When compiling u-boot with W=1 the extern inline void for
read* is likely causing the most noise. gcc / clang will
warn there is never a actual declaration for these functions.
Instead of declaring these extern make them static inline so
it is actually declared.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
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|
| 6defdc0b | 29-Aug-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-ti |
| 7f14fb20 | 29-Aug-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze |
| 5ddc3293 | 29-Aug-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-tegra |
| 5a1095a8 | 29-Aug-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx |
| 6af857c5 | 29-Aug-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of http://git.denx.de/u-boot-sunxi |
| 3e1b36bd | 28-Aug-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arm |
| 61f66fd5 | 25-Jul-2014 |
Vitaly Andrianov <vitalya@ti.com> |
keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.
Acked-
keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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|
| 9352697a | 22-Jul-2014 |
pekon gupta <pekon@ti.com> |
board/ti/dra7xx: add support for parallel NOR
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and
board/ti/dra7xx: add support for parallel NOR
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.
As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
SW5.1 (NAND_BOOTn) = OFF (logic-1)
SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */
SW5.3 (eMMC_BOOTn) = OFF (logic-1)
SW5.4 (QSPI_BOOTn) = OFF (logic-1)
And also set appropriate SYSBOOT configurations:
SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */
SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */
SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */
SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */
Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:
show more ...
|
| d145878d | 15-Aug-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6sxsabresd: Add Ethernet support
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.
Add support for one FEC port initially.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale
mx6sxsabresd: Add Ethernet support
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.
Add support for one FEC port initially.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
show more ...
|
| 68968901 | 03-Aug-2014 |
Marek Vasut <marex@denx.de> |
ARM: mx5: Fix CHSCCDR name
Fix the name of the CCM CHSCCDR register.
Signed-off-by: Marek Vasut <marex@denx.de> |