Exynos5800: Introduce new proid for Exynos5800

This patch intends to add a new proid for Exynos5800 which is a
variant of Exynos5420. Product id for Exynos5800 is 0x5422.
Both Exynos5420 and Exynos5

Exynos5800: Introduce new proid for Exynos5800

This patch intends to add a new proid for Exynos5800 which is a
variant of Exynos5420. Product id for Exynos5800 is 0x5422.
Both Exynos5420 and Exynos5800 are pin to pin compitable. This
gives us an advantage of reusing Exynos5420 clock, pinmux, memory
and other settings.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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imx:mx6slevk add board level support for usb

Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6slevk board:
1. otg port
2. host port
The following

imx:mx6slevk add board level support for usb

Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to let host port work in host mode.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <B37916@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-sunxi

Merge branch 'master' of git://git.denx.de/u-boot-arm

sun6i: ehci: Add sun6i ehci support

Add support for the 2 ehci controllers found on the sun6i (A31) soc.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.u

sun6i: ehci: Add sun6i ehci support

Add support for the 2 ehci controllers found on the sun6i (A31) soc.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Marek Vasut <marex@denx.de>

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sun6i: Add dram initialization code

Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).

This is based

sun6i: Add dram initialization code

Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).

This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sun4i: Rename dram files to dram_sun4i.x

In preparation for adding sun6i dram support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

sun6i: Add cpucfg register definitions

Not used atm, for future use (e.g. PSCI).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

sun6i: Add clock functions needed for SPL / DRAM init

Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).

Also add so

sun6i: Add clock functions needed for SPL / DRAM init

Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).

Also add some extra clock register constant defines.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sun6i: Add new p2wi controller driver

The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, t

sun6i: Add new p2wi controller driver

The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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ARM: cache-cp15: Use more accurate types

size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so u

ARM: cache-cp15: Use more accurate types

size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
the system is 64-bit or uses a form of physical address extension to use
a larger address space on 32-bit systems. Using these types the same API
can be implemented on a wider range of systems.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

ARM: UniPhier: add set_pinsel macro for use in assembly code

The function sg_set_pinsel is useful for switching I/O pins
but it can be only used in C code. This commit adds a simple
macro that is a

ARM: UniPhier: add set_pinsel macro for use in assembly code

The function sg_set_pinsel is useful for switching I/O pins
but it can be only used in C code. This commit adds a simple
macro that is available in asm code.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

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usb: UniPhier: add UniPhier on-chip EHCI host driver support

Support EHCI host driver used on Panasonic UniPhier platform.
Since Device Tree is not supported on UniPhier yet, the base address
of USB

usb: UniPhier: add UniPhier on-chip EHCI host driver support

Support EHCI host driver used on Panasonic UniPhier platform.
Since Device Tree is not supported on UniPhier yet, the base address
of USB cores are passed from board files (platdevice.c).

TODO for me:
Move the base address to device trees.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>

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ARM: UniPhier: add MIO register file

This commit adds register defines of MIO (Media I/O) block
of UniPhier platform. This file is necessary to control
the reset signals of the USB cores.

Signed-o

ARM: UniPhier: add MIO register file

This commit adds register defines of MIO (Media I/O) block
of UniPhier platform. This file is necessary to control
the reset signals of the USB cores.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

arm: rmobile: Move rcar-i2c of the address defined to common header

R-Car SoCs of rmobile have same IP of rcar-i2c, and have same address.
This moves rcar-i2c of the address defined to rcar-base.h a

arm: rmobile: Move rcar-i2c of the address defined to common header

R-Car SoCs of rmobile have same IP of rcar-i2c, and have same address.
This moves rcar-i2c of the address defined to rcar-base.h as common header of
R-Car SoCs.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

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arm: rmobile: Move sh-i2c of the address defined to common header

R-Car SoCs of rmobile have same IP of sh-i2c, and have same address.
This moves sh-i2c of the address defined to rcar-base.h as comm

arm: rmobile: Move sh-i2c of the address defined to common header

R-Car SoCs of rmobile have same IP of sh-i2c, and have same address.
This moves sh-i2c of the address defined to rcar-base.h as common header of
R-Car SoCs, and headers of each SoCs.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

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arm: rmobile: Add support R8A7793

Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamur

arm: rmobile: Add support R8A7793

Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

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Merge git://git.denx.de/u-boot-ti

arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Pre

arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI
driver is enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>

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arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the ne

arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.

Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.

One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.

Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>

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am335x: make get_board_rev() function weak

Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct impl

am335x: make get_board_rev() function weak

Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this
function weak.
In addition open code the trivial and useless BOARD_REV_ID define and
adjust the comment.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>

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Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh

net: keystone_net: add Keystone2 K2L SoC support

The Keystone2 Lamar SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2L SoCs.

Acked-by: Murali Karicheri <m-karicher

net: keystone_net: add Keystone2 K2L SoC support

The Keystone2 Lamar SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2L SoCs.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

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