| 9d4b7d0b | 09-Nov-2014 |
Hans de Goede <hdegoede@redhat.com> |
sun4i: Rename dram_clk_cfg to dram_clk_gate
The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a
dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on
sun6i, so
sun4i: Rename dram_clk_cfg to dram_clk_gate
The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a
dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on
sun6i, so name it the same on sun4i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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|
| c207ff61 | 17-Oct-2014 |
Alison Wang <b18965@freescale.com> |
arm: ls102xa: Remove bit reversing for SCFG registers
SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other
arm: ls102xa: Remove bit reversing for SCFG registers
SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.
Address: 157_0000h base + 200h offset = 157_0200h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31
This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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|
| 644bc7ec | 17-Oct-2014 |
Jason Jin <Jason.Jin@freescale.com> |
arm: ls102xa: Add snoop disable for slave port 0, 1 and 2
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by: Jason Jin <Jason.Jin@freescale
arm: ls102xa: Add snoop disable for slave port 0, 1 and 2
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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|
| 3f041f01 | 17-Oct-2014 |
Nikhil Badola <nikhil.badola@freescale.com> |
drivers: usb: fsl: Define USB configs for LS102XA
Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT
Signed-off-by: Nikhil Badola <nikhil.badola@frees
drivers: usb: fsl: Define USB configs for LS102XA
Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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|
| dee332ff | 24-Nov-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx |
| 1739564e | 24-Nov-2014 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-dm
Conflicts:
drivers/serial/serial-uclass.c
Signed-off-by: Tom Rini <trini@ti.com> |
| 8d29cef5 | 21-Nov-2014 |
Nikita Kiryanov <nikita@compulab.co.il> |
arm: mx6: introduce disable_sata_clock
Implement disable_sata_clock for mx6 SoCs.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de> |
| cf202d26 | 20-Nov-2014 |
Nitin Garg <nitin.garg@freescale.com> |
mx6: clock: Add thermal clock enable function
Add api to check and enable pll3 as required
for thermal sensor driver.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.ga
mx6: clock: Add thermal clock enable function
Add api to check and enable pll3 as required
for thermal sensor driver.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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|
| 0f65f48b | 29-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: at91: Add driver model support for the serial driver
Add driver model support while retaining the existing legacy code. This
allows the driver to support boards that have converted to driver mod
dm: at91: Add driver model support for the serial driver
Add driver model support while retaining the existing legacy code. This
allows the driver to support boards that have converted to driver model
as well as those that have not.
Signed-off-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 12fe7f7c | 29-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: at91: Add platform data for GPIO on at91sam9260-based boards
These boards all have the same GPIO arrangement, so add some common platform
data that can be used by all boards. Remove the configs
dm: at91: Add platform data for GPIO on at91sam9260-based boards
These boards all have the same GPIO arrangement, so add some common platform
data that can be used by all boards. Remove the configs which are no longer
required.
Signed-off-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 918354b1 | 29-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: at91: Add driver model support for atmel GPIO driver
Modify this driver to support driver model, with platform data required to
determine the GPIOs that it controls.
Signed-off-by: Simon Glass
dm: at91: Add driver model support for atmel GPIO driver
Modify this driver to support driver model, with platform data required to
determine the GPIOs that it controls.
Signed-off-by: Simon Glass <sjg@chromium.org>
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|
| 5d7b131d | 06-Nov-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: remove CONFIG_ARM926EJS defines
CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CO
ARM: remove CONFIG_ARM926EJS defines
CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CONFIG_ARM926EJS and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
show more ...
|
| f2168440 | 06-Nov-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: remove CONFIG_ARM920T defines
CONFIG_CPU_ARM920T was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CONFIG
ARM: remove CONFIG_ARM920T defines
CONFIG_CPU_ARM920T was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).
This commit removes all the defines of CONFIG_ARM920T and replaces the
only reference in drivers/usb/host/ohci-hcd.c with CONFIG_CPU_ARM920T.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
show more ...
|
| 3fcfe803 | 06-Nov-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
ARM: remove CONFIG_ARMV7 defines
Some (not all) of ARMv7 boards define CONFIG_ARMV7, which is useless.
Besides, it is never referenced.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Ac
ARM: remove CONFIG_ARMV7 defines
Some (not all) of ARMv7 boards define CONFIG_ARMV7, which is useless.
Besides, it is never referenced.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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|
| 573960ac | 14-Nov-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: add weim registers
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
| 32c81ea6 | 14-Nov-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
imx: consolidate set_chipselect_size function
Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.
While doing th
imx: consolidate set_chipselect_size function
Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.
While doing this the iomuxc gpr member needed to be consolidated between
MX5 and MX6.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
show more ...
|
| d8222dbe | 09-Oct-2014 |
Tang Yuantian <Yuantian.Tang@freescale.com> |
arm: ls102xa: Fixed a register definition error
There are 8 SCFG_SPARECR registers in SCFG memory block, not one.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <y
arm: ls102xa: Fixed a register definition error
There are 8 SCFG_SPARECR registers in SCFG memory block, not one.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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|
| 93d33204 | 25-Sep-2014 |
Zhao Qiang <B45475@freescale.com> |
qe: add u-qe support to arm board
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
[York Sun: Fix compiling error cause
qe: add u-qe support to arm board
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun <yorksun@freescale.com>
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|
| 927b901b | 10-Nov-2014 |
Bo Shen <voice.shen@atmel.com> |
ARM: atmel: add sama5d4ek board support
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display
- Support ethernet
- Sup
ARM: atmel: add sama5d4ek board support
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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|
| 5abc00d0 | 31-Oct-2014 |
Heiko Schocher <hs@denx.de> |
arm, spl, at91: add at91sam9260 and at91sam9g45 spl support
add support for using spl code on at91sam9260 and at91sam9g45
based boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Sh
arm, spl, at91: add at91sam9260 and at91sam9g45 spl support
add support for using spl code on at91sam9260 and at91sam9g45
based boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[adopt Bo's change in spl.c]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
show more ...
|
| bd1bb3c6 | 31-Oct-2014 |
Heiko Schocher <hs@denx.de> |
arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.deve
arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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|
| 256d83cd | 17-Nov-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh |
| 6a23c653 | 29-Oct-2014 |
Suriyan Ramasami <suriyan.r@gmail.com> |
arm: odroid: usb: add support for usb host including ethernet
This change adds support for enabling the USB host features of the board.
This includes the USB3503A hub and the SMC LAN9730 ethernet co
arm: odroid: usb: add support for usb host including ethernet
This change adds support for enabling the USB host features of the board.
This includes the USB3503A hub and the SMC LAN9730 ethernet controller
as well.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
show more ...
|
| bdba1328 | 29-Oct-2014 |
Suriyan Ramasami <suriyan.r@gmail.com> |
arm: odroid: enable/disable usb host phy for exynos4412
Enable/disable the usb host phy on the odroid U/X2 boards which are based
on the Exynos4412 SOC.
Signed-off-by: Suriyan Ramasami <suriyan.r@g
arm: odroid: enable/disable usb host phy for exynos4412
Enable/disable the usb host phy on the odroid U/X2 boards which are based
on the Exynos4412 SOC.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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|
| 06109109 | 13-Nov-2014 |
Alim Akhtar <alim.akhtar@samsung.com> |
DMC: Exynos5: Enable update mode for DREX controller
As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. An
DMC: Exynos5: Enable update mode for DREX controller
As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
show more ...
|