| e954eb80 | 17-Sep-2015 |
Bernhard Nortmann <bernhard.nortmann@web.de> |
sunxi: move SPL-related definitions to platform-specific include
The sunxi platform currently doesn't seem to make any use of the
asm/arch-sunxi/spl.h file. This patch moves some declarations from
t
sunxi: move SPL-related definitions to platform-specific include
The sunxi platform currently doesn't seem to make any use of the
asm/arch-sunxi/spl.h file. This patch moves some declarations from
tools/mksunxiboot.c into it.
This enables us to reuse those definitions when extending the
sunxi board code (boards/sunxi/boards.c).
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
|
| 1090a56c | 12-Sep-2015 |
Simon Glass <sjg@chromium.org> |
arm: Drop old non-generic-board code
This code is no-longer used. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@gmail.com> |
| f7ca45e8 | 10-Sep-2015 |
Peter Griffin <peter.griffin@linaro.org> |
ARM: hi6220: Add UART0 and UART3 base addresses
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org> |
| 8e1601d9 | 08-Sep-2015 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up a
ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| aba11d44 | 08-Sep-2015 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up a
ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| c043c025 | 20-Aug-2015 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra: Implement clk_m
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restricti
ARM: tegra: Implement clk_m
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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|
| a6b2daff | 11-Mar-2015 |
Axel Lin <axel.lin@ingics.com> |
tegra: Remove tegra_spl_gpio_direction_output declaration from header file
This function is deleted by commit 2fccd2d96bad
"tegra: Convert tegra GPIO driver to use driver model".
Signed-off-by: Axe
tegra: Remove tegra_spl_gpio_direction_output declaration from header file
This function is deleted by commit 2fccd2d96bad
"tegra: Convert tegra GPIO driver to use driver model".
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 68282f55 | 14-Sep-2015 |
Stefan Roese <sr@denx.de> |
arm: Remove unused ST-Ericsson u8500 arch
This arch does not seem to be supported / used at all in the current
U-Boot mainline source tree any more. So lets remove the core u8500 code
and code that
arm: Remove unused ST-Ericsson u8500 arch
This arch does not seem to be supported / used at all in the current
U-Boot mainline source tree any more. So lets remove the core u8500 code
and code that was only referenced by this platform.
Please note that this patch also removes these config options:
- CONFIG_PL011_SERIAL_RLCR
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT
As they only seem to be referenced by u8500 based boards. Without any
such board in the current code, these config option don't make sense
any more. Lets remove them as well.
If someone still wants to use this platform, then please send patches
to re-enable support by adding at least one board that references this
code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 850f7887 | 13-Sep-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh |
| 1a8150d4 | 03-Sep-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: mx7dsabresd: Add support for MX7D SABRESD board
* Add i.MX7D SABRESD target board support with enabled modules:
UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.
Build target: mx7dsabres
imx: mx7dsabresd: Add support for MX7D SABRESD board
* Add i.MX7D SABRESD target board support with enabled modules:
UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.
Build target: mx7dsabresd_config
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
show more ...
|
| 648539c9 | 02-Sep-2015 |
Adrian Alonso <aalonso@freescale.com> |
arm: imx-common: init: rework wdog settings for imx6/imx7
Rework imx_set_wdog_powerdown to be reused by imx6 and imx7
Signed-off-by: Adrian Alonso <aalonso@freescale.com> |
| c5752f73 | 02-Sep-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: imx7d: Add SoC system support
Add imx7d basic SoC system support
Misc arch dependent functions for system bring up
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan
imx: imx7d: Add SoC system support
Add imx7d basic SoC system support
Misc arch dependent functions for system bring up
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
show more ...
|
| 7bebc4b0 | 02-Sep-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: imx7d: clock control module support
* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
root frequency generation denominated clock slic
imx: imx7d: clock control module support
* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
root frequency generation denominated clock slices.
Core clock slice: hihg speed clock for ARM core
Bus clock slice: for bus clocks
IP clock slice: Peripheral clocks
* At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
In u-boot, we have to:
- Configure PFD3- PFD7 for freq we needed in u-boot
- Set clock root for peripherals (ip channel)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
show more ...
|
| b1d902a9 | 02-Sep-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: imx7d: initial arch level support
* Add system arch level header files
- imx-regs.h: iMX7D SoC system architecture registers
- crm_regs.h: Clock control module registers
- sys_proto.h: he
imx: imx7d: initial arch level support
* Add system arch level header files
- imx-regs.h: iMX7D SoC system architecture registers
- crm_regs.h: Clock control module registers
- sys_proto.h: helper callback function for SoC setup
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
show more ...
|
| 69535741 | 02-Sep-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: system counter driver for imx7d and mx6ul
Add system counter driver for imx7d and mx6ul
imx7 and imx6ul supports system counter timer as well as
GPT timer (arch/arm/imx-common/timer.c); The def
imx: system counter driver for imx7d and mx6ul
Add system counter driver for imx7d and mx6ul
imx7 and imx6ul supports system counter timer as well as
GPT timer (arch/arm/imx-common/timer.c); The default for
imx7 is systemcounter timer.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
show more ...
|
| 50a082a8 | 02-Sep-2015 |
Adrian Alonso <aalonso@freescale.com> |
arm: imx: imx-common: init: move arch init common setup
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.
Signed-off-by: Adrian
arm: imx: imx-common: init: move arch init common setup
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
show more ...
|
| 15c52b3d | 02-Sep-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: arch-mx6: add is_soc_type helper macro
Add helper macro is_soc_type to identify iMX SoC family
Signed-off-by: Adrian Alonso <aalonso@freescale.com> |
| 89983478 | 09-Sep-2015 |
Sylvain Lemieux <slemieux@tycoint.com> |
gpio: lpc32xx: fix issues with port3 gpio
The current simplify lpc32xx gpio driver implementation assume a
maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO
and 6 GPIO to managed on p
gpio: lpc32xx: fix issues with port3 gpio
The current simplify lpc32xx gpio driver implementation assume a
maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO
and 6 GPIO to managed on port 3.
Update the driver to fix the following:
1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number)
the second call to "gpio_request" will return -EBUSY.
2) The status of GPO_xx pin report the status of the
corresponding GPI_xx pin when using the "gpio status" command.
3) The gpio driver may setup the direction register for the wrong
gpio when calling "gpio_direction_input" (GPI_xx) or
"gpio_direction_output" (GPO_xx) on port 3; the call to the
direction is require to use the "gpio status" command.
The following change were done in the driver:
1) port3 GPI are cache in a separate 32 bits in the array.
2) port3 direction register written only for GPIO pins.
3) port3 GPO & GPIO (as output) are read using "p3_outp_state".
4) LPC32XX_GPI_P3_GRP updated to match the change.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
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|
| 92a3188d | 07-Sep-2015 |
Heiko Schocher <hs@denx.de> |
bitops: introduce BIT() definition
introduce BIT() definition, used in at91_udc gadget
driver.
Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-
bitops: introduce BIT() definition
introduce BIT() definition, used in at91_udc gadget
driver.
Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
show more ...
|
| da53ba02 | 02-Sep-2015 |
Stefan Roese <sr@denx.de> |
arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4
This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be n
arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4
This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
switch between both ECC schemes for backwards compatibility.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
show more ...
|
| 7495e41b | 31-Aug-2015 |
Simon Glass <sjg@chromium.org> |
arm: Remove snowball and u8500_href boards
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org> |
| af7f884b | 31-Aug-2015 |
Simon Glass <sjg@chromium.org> |
arm: Remove eukrea boards
These boards have not been converted to generic board by the deadline.
Remove all cpu9260 and cpuat91 boards.
Signed-off-by: Simon Glass <sjg@chromium.org> |
| 679d4456 | 31-Aug-2015 |
Simon Glass <sjg@chromium.org> |
arm: Remove balloon3 board
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org> |
| bab8d1e2 | 27-Aug-2015 |
Vladimir Zapolskiy <vz@mleia.com> |
lpc32xx: remove duplicated DMA_CLK_ENABLE bit definition
Because there is an originally defined CLK_DMA_ENABLE macro in clk.h,
no reason to add another DMA_CLK_ENABLE macro with the same value.
Rem
lpc32xx: remove duplicated DMA_CLK_ENABLE bit definition
Because there is an originally defined CLK_DMA_ENABLE macro in clk.h,
no reason to add another DMA_CLK_ENABLE macro with the same value.
Remove DMA_CLK_ENABLE, since it does not follow naming convention from
the code, this implies renaming of DMA_CLK_ENABLE to CLK_DMA_ENABLE in
lpc32xx/devices.c file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
show more ...
|
| c9feb427 | 03-Sep-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-rockchip |