imx: mx6: crm_reg: add LCDIF related macros

Add i.MX6UL/SX LCDIF related macros. Discard uneccessary
'#ifdef xxx'.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de

imx: mx6: crm_reg: add LCDIF related macros

Add i.MX6UL/SX LCDIF related macros. Discard uneccessary
'#ifdef xxx'.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>

show more ...

imx: mx6: fix register address

1. Move WDOG3_BASE_ADDR to '#if !(defined(__ASSEMBLY__))'.
2. Add i.MX6UL LCDIF register base address. And Introduce
LCDIF1_BASE_ADDR to support runtime check.
3. i

imx: mx6: fix register address

1. Move WDOG3_BASE_ADDR to '#if !(defined(__ASSEMBLY__))'.
2. Add i.MX6UL LCDIF register base address. And Introduce
LCDIF1_BASE_ADDR to support runtime check.
3. include <asm/imx-common/regs-lcdif.h> for imx-regs.h to avoid
building error for mxsfb.c, since mxsfb.c use imx-regs.h.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

show more ...

imx: lcdif: use one register structure for i.MXes

Share one lcdif structure for i.MXes.
1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7
2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-

imx: lcdif: use one register structure for i.MXes

Share one lcdif structure for i.MXes.
1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7
2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-common

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

show more ...

imx: imx-common: move lcdif structure and macro definition to imx-common

Move 'struct mxs_lcdif_regs' and lcdif related macro definitions to
arch/arm/include/asm/imx-common/regs-lcdif.h.

Signed-off

imx: imx-common: move lcdif structure and macro definition to imx-common

Move 'struct mxs_lcdif_regs' and lcdif related macro definitions to
arch/arm/include/asm/imx-common/regs-lcdif.h.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

show more ...

imx: include linux/types.h for regs-common.h

There are uint8_t, uint32_t types in regs-common.h, so include
linux/types.h.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic

imx: include linux/types.h for regs-common.h

There are uint8_t, uint32_t types in regs-common.h, so include
linux/types.h.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

show more ...

mxs: regs-common.h must be wrapped with !__ASSEMBLY__

regs-common.h must be wrapped with #ifndef __ASSEMBLY__

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

mxs: add parameter base_addr for mxs_set_lcdclk

Change mxs_set_lcdclk prototype to add a new parameter
base_addr. There are two LCD interfaces for i.MX6SX,
we may support LCDIF1 or LCDIF2.

Signed-o

mxs: add parameter base_addr for mxs_set_lcdclk

Change mxs_set_lcdclk prototype to add a new parameter
base_addr. There are two LCD interfaces for i.MX6SX,
we may support LCDIF1 or LCDIF2.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>

show more ...

mx7: psci: add basic psci support

1. add basic psci support for imx7 chip.
2. support cpu_on and cpu_off.
3. switch to non-secure mode when boot linux kernel.
4. set csu allow accessing all peripher

mx7: psci: add basic psci support

1. add basic psci support for imx7 chip.
2. support cpu_on and cpu_off.
3. switch to non-secure mode when boot linux kernel.
4. set csu allow accessing all peripherial register in non-secure mode.

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

show more ...

ARM: tegra: rename GPU functions

Rename GPU functions to less generic names to avoid potential name
collisions.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Stephen Warren <swar

ARM: tegra: rename GPU functions

Rename GPU functions to less generic names to avoid potential name
collisions.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

show more ...

ARM: tegra: remove vpr_configured() function

There is no justification for this function, especially in exported
form.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Tom Warr

ARM: tegra: remove vpr_configured() function

There is no justification for this function, especially in exported
form.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

show more ...

Merge git://git.denx.de/u-boot

armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY

The implementation of noncached_init() uses define MMU_SECTION_SIZE.
Define this on ARM64.

Move the prototype of noncached_{init,alloc}()

armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY

The implementation of noncached_init() uses define MMU_SECTION_SIZE.
Define this on ARM64.

Move the prototype of noncached_{init,alloc}() to a location that
doesn't depend on !defined(CONFIG_ARM64).

Note that noncached_init() calls mmu_set_region_dcache_behaviour() which
relies on something having set up translation tables with 2MB block size.
The core ARMv8 MMU setup code does not do this by default, but currently
relies on SoC specific MMU setup code. Be aware of this before enabling
this feature on your platform!

Signed-off-by: Stephen Warren <swarren@nvidia.com>

show more ...

arm: stm32f4: fix a bug when a random sector gets erased

Old sector number is not being cleared from FLASH_CR register. For example
when first erased sector was 001 and then you want to erase sector

arm: stm32f4: fix a bug when a random sector gets erased

Old sector number is not being cleared from FLASH_CR register. For example
when first erased sector was 001 and then you want to erase sector 010,
sector 011 gets erased instead.
This patch clears old sector number from FLASH_CR register before a new
one is written.

Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>

show more ...

arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD

When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, wh

arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD

When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.

This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>

show more ...

ARM64: zynqmp: Sync zynq_sdhci_init() declaration

This patch fix compilation error:
drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for
‘zynq_sdhci_init’
int zynq_sdhci_init(phys_addr_t reg

ARM64: zynqmp: Sync zynq_sdhci_init() declaration

This patch fix compilation error:
drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for
‘zynq_sdhci_init’
int zynq_sdhci_init(phys_addr_t regbase)
^
In file included from drivers/mmc/zynq_sdhci.c:14:0:
./arch/arm/include/asm/arch/sys_proto.h:16:5: note: previous declaration
of ‘zynq_sdhci_init’ was here
int zynq_sdhci_init(unsigned long regbase);
^

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

show more ...

ARM: Use the generic bitops headers

The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-

ARM: Use the generic bitops headers

The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>

show more ...

imx: hab: add secure boot fuse details

Add secure boot fuse helper struct to abstract the way
to find out secure boot settings per SoC iMX family

Signed-off-by: Adrian Alonso <aalonso@freescale.com>

imx: hab: use unified rom section for mx6sx and mx6ul

Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target
platforms to resolve corresponding HAB_RVT_BASE base address,
the RVT table contains

imx: hab: use unified rom section for mx6sx and mx6ul

Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target
platforms to resolve corresponding HAB_RVT_BASE base address,
the RVT table contains pointers to the HAB API functions in
ROM code.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>

show more ...

imx: hab: rework secure boot support for imx6

Rework secure boot support for imx6, move existing hab support
for imx6 into imx-common for SoC reuse.

Signed-off-by: Adrian Alonso <aalonso@freescale.

imx: hab: rework secure boot support for imx6

Rework secure boot support for imx6, move existing hab support
for imx6 into imx-common for SoC reuse.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>

show more ...

imx: cpu: move common chip revision id's

Move common chip revision id's to main cpu header file
mx25 generic include cpu header for chip revision

Signed-off-by: Adrian Alonso <aalonso@freescale.com>

arm, imx: add some gpr register defines

add some missing gpr register defines.

Signed-off-by: Heiko Schocher <hs@denx.de>

arm: ls1021a: Add sata support on qds and twr board

Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification

arm: ls1021a: Add sata support on qds and twr board

Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

armv8/fsl_lsch2: Add fsl_lsch2 SoC

Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.

Signed-off-by: Li Yang <leoli@freescale.com>
Signe

armv8/fsl_lsch2: Add fsl_lsch2 SoC

Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

armv8/fsl_lsch3: Change arch to fsl-layerscape

There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use

armv8/fsl_lsch3: Change arch to fsl-layerscape

There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...

armv7/ls1021a: move ns_access to common file

Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by:

armv7/ls1021a: move ns_access to common file

Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...