| #
ba6a1698 |
| 19-Sep-2013 |
Andre Przywara <andre.przywara@linaro.org> |
ARM: add SMP support for non-secure switch
Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure stat
ARM: add SMP support for non-secure switch
Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address.
The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board.
The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
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| #
1ef92385 |
| 19-Sep-2013 |
Andre Przywara <andre.przywara@linaro.org> |
ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we n
ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards.
We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable.
Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF)
The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
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| #
16212b59 |
| 19-Sep-2013 |
Andre Przywara <andre.przywara@linaro.org> |
ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the
ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable.
Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF)
Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register.
The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here.
After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
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| #
d75ba503 |
| 19-Sep-2013 |
Andre Przywara <andre.przywara@linaro.org> |
ARM: prepare armv7.h to be included from assembly source
armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriat
ARM: prepare armv7.h to be included from assembly source
armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
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| #
326ea986 |
| 31-Jul-2013 |
Stefano Babic <sbabic@denx.de> |
Merge git://git.denx.de/u-boot-arm
Conflicts: board/freescale/mx6qsabrelite/Makefile board/freescale/mx6qsabrelite/mx6qsabrelite.c include/configs/mx6qsabrelite.h
Signed-off-by: Stefano Babic <s
Merge git://git.denx.de/u-boot-arm
Conflicts: board/freescale/mx6qsabrelite/Makefile board/freescale/mx6qsabrelite/mx6qsabrelite.c include/configs/mx6qsabrelite.h
Signed-off-by: Stefano Babic <sbabic@denx.de>
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| #
8b485ba1 |
| 25-Jul-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into u-boot-arm/master
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| #
1a459660 |
| 08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
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| #
0ce033d2 |
| 18-Mar-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard
Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard being added to in mainline and enhanced in u-boot-arm/master with proper formatting.
Conflicts: arch/arm/cpu/ixp/u-boot.lds arch/arm/cpu/u-boot.lds arch/arm/lib/Makefile board/actux1/u-boot.lds board/actux2/u-boot.lds board/actux3/u-boot.lds board/dvlhost/u-boot.lds board/freescale/mx31ads/u-boot.lds doc/README.scrapyard include/configs/tegra-common.h
Build tested for all of ARM and run-time tested on am335x_evm.
Signed-off-by: Tom Rini <trini@ti.com>
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| #
eed7c0f7 |
| 12-Feb-2013 |
SRICHARAN R <r.sricharan@ti.com> |
ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.c
ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
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| #
0e62e0a7 |
| 16-Nov-2011 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: arm, davinci: add DAVINCI_MMC_CLKID arm, davinci_emac: fix driver bug if more then 3 PHYs ar
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: arm, davinci: add DAVINCI_MMC_CLKID arm, davinci_emac: fix driver bug if more then 3 PHYs are detected arm, davinci: da850/dm365 lowlevel cleanup omap5: Add omap5_evm board build support. omap4/5: Add support for booting with CH. omap5: emif: Add emif/ddr configurations required for omap5 evm omap5: clocks: Add clocks support for omap5 platform. omap5: Add minimal support for omap5430. omap: Checkpatch fixes omap4: make omap4 code common for future reuse GCC4.6: Squash warnings in onenand_base.c GCC4.6: Fix common/usb.c on xscale OneNAND: Add simple OneNAND SPL PXA: vpac270: Enable the new generic MMC driver PXA: Cleanup serial_pxa PXA: Drop csb226 and innokom boards (unmaintained) m28evk: Fix comment about the number of RAM banks mx31: Fix checkpatch warnings in generic.c mx31: Use proper IO accessor for GPR register mx31: Remove duplicate definition for GPR register qong: Use generic function for configuring GPR register M28EVK: Enable USB HOST support iMX28: Add USB HOST driver iMX28: Add USB and USB PHY register definitions M28: Add memory detection into SPL iMX28: Fix ARM vector handling M28: Add doc/README.m28 documentation M28: Add MMC SPL iMX28: Add support for DENX M28EVK board iMX28: Add u-boot.sb target to Makefile iMX28: Add image header generator tool iMX28: Add driver for internal RTC iMX28: Add GPMI NAND driver iMX28: Add APBH DMA driver iMX28: Add SPI driver iMX28: Add GPIO control iMX28: Add I2C bus driver iMX28: Add PINMUX control FEC: Add support for iMX28 quirks iMX28: Add SSP MMC driver iMX28: Initial support for iMX28 CPU MX25: zmx25: GCC4.6 fix build warnings da850: add new config file for AM18xx BeagleBoard: config: Switch to ttyO2 OMAP3: Change omap3_evm maintainer devkit8000: Fix NAND SPL on boards with 256MB NAND integrator: enable Vpp and disable flash protection integrator: add system controller header integrator: make flash writeable on boot integrator: use io-accessors for board init integrator: move text offset to config integrator: pass configs for core modules ARM: remove superfluous setting of arch_number in board specific code. SPL: Allow ARM926EJS to avoid compiling in the CPU support code integrator: do not test first part of the memory arm: a320: fix broken timer ARM: define CONFIG_MACH_TYPE for all ronetix boards dm646x: pass board revision info to kernel dm646x: add new configuration for dm6467T arm, davinci: Fix setting of the SDRAM configuration register arm, davinci: Remove the duplication of LPSC functions arm, davinci: Rename AM1808 lowlevel functions to DA850 da8xxevm: fix build error ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE
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| #
0c2dd9a0 |
| 16-Nov-2011 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: arm, davinci: add DAVINCI_MMC_CLKID arm, davinci_emac: fix driver bug if more then 3 PHYs are de
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: arm, davinci: add DAVINCI_MMC_CLKID arm, davinci_emac: fix driver bug if more then 3 PHYs are detected arm, davinci: da850/dm365 lowlevel cleanup omap5: Add omap5_evm board build support. omap4/5: Add support for booting with CH. omap5: emif: Add emif/ddr configurations required for omap5 evm omap5: clocks: Add clocks support for omap5 platform. omap5: Add minimal support for omap5430. omap: Checkpatch fixes omap4: make omap4 code common for future reuse GCC4.6: Squash warnings in onenand_base.c GCC4.6: Fix common/usb.c on xscale OneNAND: Add simple OneNAND SPL PXA: vpac270: Enable the new generic MMC driver PXA: Cleanup serial_pxa PXA: Drop csb226 and innokom boards (unmaintained) m28evk: Fix comment about the number of RAM banks mx31: Fix checkpatch warnings in generic.c mx31: Use proper IO accessor for GPR register mx31: Remove duplicate definition for GPR register qong: Use generic function for configuring GPR register M28EVK: Enable USB HOST support iMX28: Add USB HOST driver iMX28: Add USB and USB PHY register definitions M28: Add memory detection into SPL iMX28: Fix ARM vector handling M28: Add doc/README.m28 documentation M28: Add MMC SPL iMX28: Add support for DENX M28EVK board iMX28: Add u-boot.sb target to Makefile iMX28: Add image header generator tool iMX28: Add driver for internal RTC iMX28: Add GPMI NAND driver iMX28: Add APBH DMA driver iMX28: Add SPI driver iMX28: Add GPIO control iMX28: Add I2C bus driver iMX28: Add PINMUX control FEC: Add support for iMX28 quirks iMX28: Add SSP MMC driver iMX28: Initial support for iMX28 CPU MX25: zmx25: GCC4.6 fix build warnings da850: add new config file for AM18xx BeagleBoard: config: Switch to ttyO2 OMAP3: Change omap3_evm maintainer devkit8000: Fix NAND SPL on boards with 256MB NAND integrator: enable Vpp and disable flash protection integrator: add system controller header integrator: make flash writeable on boot integrator: use io-accessors for board init integrator: move text offset to config integrator: pass configs for core modules ARM: remove superfluous setting of arch_number in board specific code. SPL: Allow ARM926EJS to avoid compiling in the CPU support code integrator: do not test first part of the memory arm: a320: fix broken timer ARM: define CONFIG_MACH_TYPE for all ronetix boards dm646x: pass board revision info to kernel dm646x: add new configuration for dm6467T arm, davinci: Fix setting of the SDRAM configuration register arm, davinci: Remove the duplication of LPSC functions arm, davinci: Rename AM1808 lowlevel functions to DA850 da8xxevm: fix build error ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE
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| #
508a58fa |
| 15-Nov-2011 |
Sricharan <r.sricharan@ti.com> |
omap5: Add minimal support for omap5430.
This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430.
OMAP5430 is Texas Instrument's SO
omap5: Add minimal support for omap5430.
This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430.
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency.
Also moved some part of code from the basic platform support that can be made common for OMAP4/5. Rest is kept out seperately. The same approach is followed for clocks and emif support in the subsequent patches.
Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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| #
fb6440ee |
| 04-Aug-2011 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: drivers/rtc: add Marvell Integrated RTC Armada100: Add Board Support for Marvell GuruPlug-Displa
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: drivers/rtc: add Marvell Integrated RTC Armada100: Add Board Support for Marvell GuruPlug-Display Armada100: MFP macro naming correction arm: auto gen asm-offsets.h for mb86r0x spear: fix build errors for spear3xx/spear600 platforms cosmetic: arm: lib/board.c: Coding Style cleanup ARM: versatile: fix board support SMDKV310: Enable device tree support SMDKV310: MMC_SPL: Fix building when using "make O=" arm: a320: enable tagged list support arm: a320: fix multiline comment style ARMv7: u8500_href: Add missing header to fix compiler warning Removed unused define, CONFIG_ARMV7. avr32: add grasshopper (ICnova AP7000) board AT91/SPI: fix atmel_dataflash_spi.c to allow building without warnings MAKEALL: remove AT91 boards that are in boards.cfg AT91: Makes AT91SAM9263-EK build correctly against u-boot-atmel/master AT91: Makes AT91SAM9263 SoC build correctly against u-boot-atmel/master AT91: Board fix for AT91SAM9261-EK AT91: SoC fix at91sam9261_matrix.h AT91: Makes AT91SAM9RL-EK build correctly against u-boot-atmel/master AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master AT91: change common at91sam9261 files to compile with new scheme AT91: fix mistake in at91sam9260_devices.c(spi1_hw_init) a/a/c/arm920t/at91/reset.c: drop obsolete CONFIG_AT91RM9200_USART README: fix arm920t/at91 path net/eth.c: drop obsolete at91rm9200 support README.at91-soc: remove AT91(RM9200) joining notice a/a/c/arm920t/cpu.c: remove CONFIG_AT91_LEGACY warning MAKEALL: remove obsolete at91rm9200 soc ARM: remove obsolete at91rm9200 omap4: clock init support for omap4460 omap4: support TPS programming omap: reuse omap3 gpio support in omap4 omap4: sdram init changes for omap4460 omap4: add omap4460 revision detection mkimage: Add OMAP boot image support omap: add MMC and FAT support to SPL omap: add basic SPL support armv7: start.S: fixes and enhancements for SPL omap4: automatic sdram detection omap4: calculate EMIF register values omap4: add sdram init support omap4: add clock support omap4: add OMAP4430 revision check omap4: cleanup pin mux data omap4: utility function to identify the context of hw init DA8xx: fix LPSC constants DA8xx: switch an enum to defines for consistency DA8xx: add MMC/SD controller addresses DaVinci EMAC: declare function for all DA8xx CPUs DA8xx: add generic GPIO driver DaVinci: rename gpio_defs.h to gpio.h omap3evm: eth: Include functions only when necessary omap3evm: Update ethernet reset sequence for Rev.G board omap3evm: eth: split function setup_net_chip omap3: Include array definition only when it is used omap730p2: fix build breaks omap2420h4: fix build breaks omap1610inn: fix build breaks omap1510inn: fix build breaks omap5912osk: fix build breaks omap1610h2: fix build breaks
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| #
5ab12a9e |
| 21-Jul-2011 |
Aneesh V <aneesh@ti.com> |
omap4: add omap4460 revision detection
Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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| #
ad577c8a |
| 21-Jul-2011 |
Aneesh V <aneesh@ti.com> |
omap4: add OMAP4430 revision check
Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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| #
2c451f78 |
| 16-Jun-2011 |
Aneesh V <aneesh@ti.com> |
armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU
- Add g
armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU
- Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache
- D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache
- Add maintenance functions for TLB, branch predictor array etc.
- Enable -march=armv7-a so that armv7 assembly instructions can be used
Signed-off-by: Aneesh V <aneesh@ti.com>
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