| #
02d50bb0 |
| 19-Jun-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMC: embed secondary core ep info into to SPMC context
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Icdb15b8664fb3467ffd55
SPMC: embed secondary core ep info into to SPMC context
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Icdb15b8664fb3467ffd55b44d1f0660457192586
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| #
a92bc73b |
| 23-Mar-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
Define SPMD PM hooks for warm boot and off events. svc_on_finish handler enters the SPMC at the entry point defined by the secondary EP
SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
Define SPMD PM hooks for warm boot and off events. svc_on_finish handler enters the SPMC at the entry point defined by the secondary EP register service. The svc_off handler notifies the SPMC that a physical core is being turned off through a notification message.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I2609a75a0c6ffb9f6313fc09553be2b29a41de59
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| #
f0d743db |
| 16-Apr-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: handle SPMC message to register secondary core entry point
Upon booting, the SPMC running on the primary core shall register the secondary core entry points to which a given secondary core bei
SPMD: handle SPMC message to register secondary core entry point
Upon booting, the SPMC running on the primary core shall register the secondary core entry points to which a given secondary core being woken up shall jump to into the SPMC . The current implementation assumes the SPMC calls a registering service implemented in the SPMD for each core identified by its MPIDR. This can typically happen in a simple loop implemented in the early SPMC initialization routines by passing each core identifier associated with an entry point address and context information. This service is implemented on top of a more generic SPMC<=>SPMD interface using direct request/response message passing as defined by the FF-A specification.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I1f70163b6b5cee0880bd2004e1fec41e3780ba35
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| #
c2901419 |
| 16-Apr-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: introduce SPMC to SPMD messages
FF-A interface to handle SPMC to SPMD direct messages requests.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.sve
SPMD: introduce SPMC to SPMD messages
FF-A interface to handle SPMC to SPMD direct messages requests.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Ia707a308c55561a31dcfa86e554ea1c9e23f862a
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| #
a334c4e6 |
| 28-Oct-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: register the SPD PM hooks
Change-Id: If88d64c0e3d60accd2638a55f9f3299ec700a8c8 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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| #
9dcf63dd |
| 28-Oct-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: enhance SPMC internal boot states
This patch adds SPMC states used by the SPMD to track SPMC boot phases specifically on secondary cores.
Change-Id: If97af7352dda7f04a8e46a56892a2aeddcfab91b
SPMD: enhance SPMC internal boot states
This patch adds SPMC states used by the SPMD to track SPMC boot phases specifically on secondary cores.
Change-Id: If97af7352dda7f04a8e46a56892a2aeddcfab91b Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
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| #
c0267cc9 |
| 28-Oct-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: entry point info get helper
This patch provides a helper to get the entry_point_info structure used by the boot CPU as it is used to initialise the SPMC context on secondary CPUs.
Change-Id:
SPMD: entry point info get helper
This patch provides a helper to get the entry_point_info structure used by the boot CPU as it is used to initialise the SPMC context on secondary CPUs.
Change-Id: I99087dc7a86a7258e545d24a2ff06aa25170f00c Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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| #
4b0695ac |
| 26-May-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "SPCI is now called PSA FF-A" into integration
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| #
662af36d |
| 07-May-2020 |
J-Alves <joao.alves@arm.com> |
SPCI is now called PSA FF-A
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA
SPCI is now called PSA FF-A
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA FF-A(in documents) or simply FFA(in code).
Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760 Signed-off-by: J-Alves <joao.alves@arm.com>
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| #
c9ff4e47 |
| 13-May-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I35c5abd9,I99e64245 into integration
* changes: SPMD: extract SPMC DTB header size from SPMD SPMD: code/comments cleanup
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| #
52696946 |
| 16-Apr-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: code/comments cleanup
As a follow-up to bdd2596d4, and related to SPM Dispatcher EL3 component and SPM Core S-EL2/S-EL1 component: update with cosmetic and coding rules changes. In addition: -
SPMD: code/comments cleanup
As a follow-up to bdd2596d4, and related to SPM Dispatcher EL3 component and SPM Core S-EL2/S-EL1 component: update with cosmetic and coding rules changes. In addition: -Add Armv8.4-SecEL2 arch detection helper. -Add an SPMC context (on current core) get helper. -Return more meaningful error return codes. -Remove complexity in few spmd_smc_handler switch-cases. -Remove unused defines and structures from spmd_private.h
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I99e642450b0dafb19d3218a2f0e2d3107e8ca3fe
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| #
bb37363b |
| 13-Mar-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "SPMD: Add support for SPCI_ID_GET" into integration
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| #
ac03ac5e |
| 12-Mar-2020 |
Max Shvetsov <maksims.svecovs@arm.com> |
SPMD: Add support for SPCI_ID_GET
This patch introduces the `SPCI_ID_GET` interface which will return the ID of the calling SPCI component. Returns 0 for requests from the non-secure world and the S
SPMD: Add support for SPCI_ID_GET
This patch introduces the `SPCI_ID_GET` interface which will return the ID of the calling SPCI component. Returns 0 for requests from the non-secure world and the SPCI component ID as specified in the manifest for secure world requests.
Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
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| #
63aa4094 |
| 11-Feb-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "spmd" into integration
* changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0
Merge changes from topic "spmd" into integration
* changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0 spec SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP SPMD: add support for an example SPM core manifest SPMD: add SPCI Beta 0 specification header file
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| #
bdd2596d |
| 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
SPMD: add SPM dispatcher based upon SPCI Beta 0 spec
This patch adds a rudimentary SPM dispatcher component in EL3. It does the following:
- Consumes the TOS_FW_CONFIG to determine properties of th
SPMD: add SPM dispatcher based upon SPCI Beta 0 spec
This patch adds a rudimentary SPM dispatcher component in EL3. It does the following:
- Consumes the TOS_FW_CONFIG to determine properties of the SPM core component - Initialises the SPM core component which resides in the BL32 image - Implements a handler for SPCI calls from either security state. Some basic validation is done for each call but in most cases it is simply forwarded as-is to the "other" security state.
Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: I7d116814557f7255f4f4ebb797d1619d4fbab590
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