| #
7303319b |
| 08-Nov-2025 |
Chris Kay <chris.kay@arm.com> |
Merge changes from topic "NUMA_AWARE_PER_CPU" into integration
* changes: docs(maintainers): add per-cpu framework into maintainers.rst feat(per-cpu): add documentation for per-cpu framework f
Merge changes from topic "NUMA_AWARE_PER_CPU" into integration
* changes: docs(maintainers): add per-cpu framework into maintainers.rst feat(per-cpu): add documentation for per-cpu framework feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2 feat(per-cpu): migrate amu_ctx to per-cpu framework feat(per-cpu): migrate spm_core_context to per-cpu framework feat(per-cpu): migrate psci_ns_context to per-cpu framework feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework feat(per-cpu): migrate rmm_context to per-cpu framework feat(per-cpu): integrate per-cpu framework into BL31/BL32 feat(per-cpu): introduce framework accessors/definers feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework docs(changelog): add scope for per-cpu framework
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| #
f708e9dd |
| 29-Jan-2025 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(per-cpu): migrate rmm_context to per-cpu framework
migrate rmm_context objects to the NUMA-aware per-cpu framework to optimize memory access and to efficiently utilize memory.
Signed-off-by: S
feat(per-cpu): migrate rmm_context to per-cpu framework
migrate rmm_context objects to the NUMA-aware per-cpu framework to optimize memory access and to efficiently utilize memory.
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com> Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I72d49c3d860dac10bd3930ce400b0199bedd887b
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| #
d5388ff9 |
| 28-Oct-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(rmmd): correct activation condition check" into integration
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| #
f8a9aa10 |
| 28-Oct-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge changes from topic "mb/lfa-rmm-test" into integration
* changes: fix(rmmd): avoid race conditions in CPU finish fix(arm): move lfa componet header to common and fix the helper chore(lfa)
Merge changes from topic "mb/lfa-rmm-test" into integration
* changes: fix(rmmd): avoid race conditions in CPU finish fix(arm): move lfa componet header to common and fix the helper chore(lfa): rename component_id to lfa_component_id
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| #
5ba2ad35 |
| 21-Oct-2025 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(rmmd): correct activation condition check
Update the activation condition in rmmd_primary_activate to ensure the function behaves correctly when the return code is zero. This change prevents pot
fix(rmmd): correct activation condition check
Update the activation condition in rmmd_primary_activate to ensure the function behaves correctly when the return code is zero. This change prevents potential issues during the activation process.
Change-Id: I94d76c1e491f114b7fb32dd85dbfcfe2f5f1d3da Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
57824063 |
| 21-Oct-2025 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(rmmd): avoid race conditions in CPU finish
Create a local copy of entry point info to prevent race conditions when accessing shared data. This change ensures that the CPU finish handler operates
fix(rmmd): avoid race conditions in CPU finish
Create a local copy of entry point info to prevent race conditions when accessing shared data. This change ensures that the CPU finish handler operates on a consistent state without interference from other threads, improving stability and reliability of the service.
Change-Id: I84fbc21672dde0f19176f63ee94afafc0084004e Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
92c0f3ba |
| 10-Oct-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "rmm-lfa" into integration
* changes: feat(arm): handle RMM ep_info during LFA feat(lfa): add helper to check LFA prime completion status feat(lfa): enable LFA of RMM
Merge changes from topic "rmm-lfa" into integration
* changes: feat(arm): handle RMM ep_info during LFA feat(lfa): add helper to check LFA prime completion status feat(lfa): enable LFA of RMM chore(lfa): use standard int return type for prime/activate callbacks feat(rmmd): add warm reset helpers for primary and secondary CPUs
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| #
22bbb59f |
| 15-Apr-2025 |
Andre Przywara <andre.przywara@arm.com> |
feat(rmmd): add warm reset helpers for primary and secondary CPUs
Introduce two helpers to support RMM warm reset, primarily for use during Live Firmware Activation:
- rmmd_primary_warm_reset(): r
feat(rmmd): add warm reset helpers for primary and secondary CPUs
Introduce two helpers to support RMM warm reset, primarily for use during Live Firmware Activation:
- rmmd_primary_warm_reset(): re-runs rmmd_setup() and rmm_init() for the primary CPU. - rmmd_secondary_warm_reset(): reinitializes secondary CPUs using rmmd_cpu_on_finish_handler(), with a spinlock to serialize access.
Change-Id: I885536aa85e395ed69069802112dcdb5063a9c19 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
ada94a82 |
| 16-Sep-2025 |
Soby Mathew <soby.mathew@arm.com> |
Merge "fix(rme): fix incorrect shift operation in rmmd" into integration
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| #
c08285cf |
| 15-Sep-2025 |
Soby Mathew <soby.mathew@arm.com> |
fix(rme): fix incorrect shift operation in rmmd
This patch fixes the shift operation in rmmd_mecid_key_update(). Also, a function name fix is made to the platform porting guide.
Change-Id: I80f0e26
fix(rme): fix incorrect shift operation in rmmd
This patch fixes the shift operation in rmmd_mecid_key_update(). Also, a function name fix is made to the platform porting guide.
Change-Id: I80f0e2653dcb5cdd7b5937506ca040b2105ca3ce Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| #
24804eeb |
| 15-Sep-2025 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I32c5be5d,I15a652a0 into integration
* changes: fix(qemu): add reason parameter to MEC update refactor(rmmd): modify MEC update call to meet FIRME
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| #
00e62ff9 |
| 03-Sep-2025 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
refactor(rmmd): modify MEC update call to meet FIRME
Previous version of MEC refresh call was not compliant with FIRME [1]. This patch modifies the call so it is compliant with the specification.
[
refactor(rmmd): modify MEC update call to meet FIRME
Previous version of MEC refresh call was not compliant with FIRME [1]. This patch modifies the call so it is compliant with the specification.
[1] https://developer.arm.com/documentation/den0149/1-0alp0/
Change-Id: I15a652a021561edca16e79d127e6f08975cf1361 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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| #
aed7dc81 |
| 08-Sep-2025 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "rmm-lfa" into integration
* changes: feat(rmmd): add RMM_RESERVE_MEMORY SMC handler feat(rmmd): add per-CPU activation token
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| #
745c129a |
| 09-Jul-2024 |
Andre Przywara <andre.przywara@arm.com> |
feat(rmmd): add RMM_RESERVE_MEMORY SMC handler
At the moment any memory required by an R-EL2 manager (RMM) needs to be known at compile time: that sets the size of the .data and .bss segments. Some
feat(rmmd): add RMM_RESERVE_MEMORY SMC handler
At the moment any memory required by an R-EL2 manager (RMM) needs to be known at compile time: that sets the size of the .data and .bss segments. Some resources depend on the particular machine this will be running on, the prime example is TF-RMM's granule array, which needs to know the maximum memory supported beforehand. Other data structures might depend on the number of CPU cores.
To provide more flexibility, but keep the memory footprint as small as possible, let's introduce some memory reservation SMC. Any RMM implementation can ask EL3 for some memory, and would get the physical address of a usable chunk of memory back. This must happen at RMM boot time, so before the RMM concluded the boot phase with the RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory again, this would not be needed for the use case of sizing platform resources, and avoids the complexity of a full-fledged memory allocator.
Add the new RMM_RESERVE_MEMORY command to the implementation defined RMM-EL3 SMC interface, both in code and documentation. The actual memory reservation is made a platform implementation, but a simple implementation is provided, which is used for the FVP platform already: it will just pick the next matching chunk of memory from the top end of the RMM carveout. This way the memory reservation will grow down from the end of the carveout, in a stack-like fashion, until it reaches the end of the RMM payload, located at the beginning of the carveout. Since secondary cores might also reserve memory at boot time, there is a spinlock to protect the simple allocation algorithm. Other platforms can choose to provide a more sophisticated reservation algorithm, for instance one taking NUMA locality into account.
This patch just provides the call, at this point there is no obligation to use the feature, although future TF-RMM versions would rely on it.
Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| #
89d979ce |
| 12-Jun-2025 |
Andre Przywara <andre.przywara@arm.com> |
feat(rmmd): add per-CPU activation token
To accommodate Live Firmware Activation (LFA), the RMM needs to preserve some state, between an old and the new copy of itself. The state which needs to be p
feat(rmmd): add per-CPU activation token
To accommodate Live Firmware Activation (LFA), the RMM needs to preserve some state, between an old and the new copy of itself. The state which needs to be preserved and its organisation would be completely under control of the RMM; it will be different between different RMM implementations and even between releases.
To keep the interface small, generic and robust, introduce an "activation token", which is an opaque 64-bit value to gets passed to each RMM as part of the boot/init phase. On the first initialisation, after a cold boot, this value would be initialised to 0. The RMM is expected to pass the actual value (for instance a pointer to a persistent data structure) back to BL31 as an additional argument of the RMM_BOOT_COMPLETE SMC call. On subsequent live activations, this updated token value gets passed to the (updated) RMM init routines, using the respective CPU registers.
Add an activation_token member to the (per-CPU) RMM context, and update its value with the value passed via the x2 register, at the RMM_BOOT_COMPLETE SMC call. Then pass that value into RMM either via x4 (on the primary core) or via x1 (on secondary cores). How the value is used or updated on the RMM side is of no further concern to BL31, it just passes the opaque value around. The TRP seems to be very jealous about the values in the first three registers, so let it ignore the value of x1 on a warmboot, to avoid a panic.
Change-Id: Ie8d96a046b74adb00e2ca5ce3b8458465bacf2b2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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0fe45f17 |
| 25-Jul-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(cm): unify RMM context" into integration
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284c01c6 |
| 04-Mar-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(cm): unify RMM context
setup_realm_context() is the de facto place to put any code that relates to the RMM's context. It is frequently updated and contains the vast majority of code. manage
refactor(cm): unify RMM context
setup_realm_context() is the de facto place to put any code that relates to the RMM's context. It is frequently updated and contains the vast majority of code. manage_extensions_realm() on the other hand is out of date and obscure.
So absorb manage_extensions_realm() and rmm_el2_context_init() into setup_realm_context().
We can also combine the write to sctlr_el2 for all worlds as they should all observe the RES1 values.
Finally, the SPSR_EL2.PAN comment in the realm copy is updated.
Change-Id: I21dccad0c13301e3249db6f6e292beb5d853563e Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| #
52413650 |
| 08-Jul-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(cm): gather per-world context management to the same place" into integration
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6eafc060 |
| 04-Mar-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(cm): gather per-world context management to the same place
The per-world calls are disparate - they get called in different places, are guarded in different ways, and the code is apart.
Si
refactor(cm): gather per-world context management to the same place
The per-world calls are disparate - they get called in different places, are guarded in different ways, and the code is apart.
Since they just need to be called once at boot, add a function that we can call from BL31 and be done with it.
Change-Id: Id0ade302e35f2b00ca37c552a53038942ab7b58e Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| #
ec56d595 |
| 15-Apr-2025 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "sm/rpkm" into integration
* changes: docs(rmmd): document the EL3-RMM IDE KM Interface feat(trp): test el3-rmm ide km interface feat(rmmd): el3-rmm ide key management
Merge changes from topic "sm/rpkm" into integration
* changes: docs(rmmd): document the EL3-RMM IDE KM Interface feat(trp): test el3-rmm ide km interface feat(rmmd): el3-rmm ide key management interface
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| #
2132c707 |
| 14-Mar-2025 |
Sona Mathew <sonarebecca.mathew@arm.com> |
feat(rmmd): el3-rmm ide key management interface
Patch introduces the EL3-RMM SMC Interface for Root Port Key management as per RFC discussed here: https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM
feat(rmmd): el3-rmm ide key management interface
Patch introduces the EL3-RMM SMC Interface for Root Port Key management as per RFC discussed here: https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface
Three IDE Key management smc calls have been added: - RMM_IDE_KEY_PROG() - RMM_IDE_KEY_SET_GO() - RMM_IDE_KEY_SET_STOP() - RMM_IDE_KM_PULL_RESPONSE()
Due to the absence of root port support in FVP, we are currently adding placeholders in this patch for the platform APIs to return success irrespective of the arguments being passed by the caller(Realms). The SMCs are guarded by `RMMD_ENABLE_IDE_KEY_PROG` build flag and is disabled by default. We expect that once the SMCs are stabilized, this build flag will not be required anymore.
Change-Id: I9411eb7787dac2a207bd14710d251503bd9626ce Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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| #
86618450 |
| 27-Mar-2025 |
Soby Mathew <soby.mathew@arm.com> |
Merge "fix(rme): do not trap access to MPAM system registers in Realm mode" into integration
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d048af0d |
| 21-Mar-2025 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
fix(rme): do not trap access to MPAM system registers in Realm mode
Change-Id: I77496ee962727687b28f71a1a15b4fe4133c613c Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
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| #
ca3f2eee |
| 26-Mar-2025 |
Soby Mathew <soby.mathew@arm.com> |
Merge "feat(rmmd): verify FEAT_MEC present before calling plat hoook" into integration
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| #
609ada96 |
| 24-Mar-2025 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
feat(rmmd): verify FEAT_MEC present before calling plat hoook
Some platforms do not support FEAT_MEC. Hence, they do not provide an interface to update the update of the key corresponding to a MECID
feat(rmmd): verify FEAT_MEC present before calling plat hoook
Some platforms do not support FEAT_MEC. Hence, they do not provide an interface to update the update of the key corresponding to a MECID.
This patch adds a condition in order to verify FEAT_MEC is present before calling the corresponding platform hook, thus preventing it from being called when the platform does not support the feature.
Change-Id: Ib1eb9e42f475e27ec31529569e888b93b207148c Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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