| #
10f8a397 |
| 27-Sep-2023 |
Amit Nagal <amit.nagal@amd.com> |
refactor(zynqmp): use common code for prepare_dtb
use common code definition and remove zynqmp local definition for prepare_dtb in dtb flows.
Change-Id: I362b90b96852e9afccc8a2e23d3b7f709280fba7 Si
refactor(zynqmp): use common code for prepare_dtb
use common code definition and remove zynqmp local definition for prepare_dtb in dtb flows.
Change-Id: I362b90b96852e9afccc8a2e23d3b7f709280fba7 Signed-off-by: Amit Nagal <amit.nagal@amd.com>
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| #
be3e0b89 |
| 03-Oct-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xilinx-console-sync" into integration
* changes: fix(xilinx): remove console error message feat(xilinx): sync macro names feat(xilinx): remove crash console unused ma
Merge changes from topic "xilinx-console-sync" into integration
* changes: fix(xilinx): remove console error message feat(xilinx): sync macro names feat(xilinx): remove crash console unused macros
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| #
f9820f21 |
| 27-Sep-2023 |
Michal Simek <michal.simek@amd.com> |
fix(xilinx): remove console error message
If console is not found there is no way where to print information about it. Currently only cdns/dcc/pl011 uarts are supported that's why remove the message
fix(xilinx): remove console error message
If console is not found there is no way where to print information about it. Currently only cdns/dcc/pl011 uarts are supported that's why remove the message which none can see anyway. But keep "else" part with comment to avoid misra c rule 15.7 violation which is also missing in Versal NET implementation.
Change-Id: I78e3baffd2288d2a4673099bf193f22029912840 Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
04a48335 |
| 27-Sep-2023 |
Michal Simek <michal.simek@amd.com> |
feat(xilinx): sync macro names
There is no reason to have platform specific macros where generic macros can be used. This is pretty much preparation step for moving console code to single location w
feat(xilinx): sync macro names
There is no reason to have platform specific macros where generic macros can be used. This is pretty much preparation step for moving console code to single location where multiple combinations can be easier to handle.
Change-Id: I4d85ddef29f5870a9ea9590d4d1564469c6eb87e Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
4593e7cb |
| 27-Sep-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xilinx-crash" into integration
* changes: feat(xilinx): used console also as crash console feat(versal-net): remove empty crash console setup
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| #
3e6b96e8 |
| 20-Sep-2023 |
Michal Simek <michal.simek@amd.com> |
feat(xilinx): used console also as crash console
CONSOLE_FLAG_CRASH should be also setup to get crash logs on the same console. Both platforms are using crash console implementation from plat/common
feat(xilinx): used console also as crash console
CONSOLE_FLAG_CRASH should be also setup to get crash logs on the same console. Both platforms are using crash console implementation from plat/common/aarch64/crash_console_helpers.S that's why there is necessary to setup CONSOLE_FLAG_CRASH. plat_crash_console_putc() implementation is saying: "int plat_crash_console_putc(char c) Prints the character on all consoles registered with the console framework that have CONSOLE_FLAG_CRASH set. Note that this is only helpful for crashes that occur after the platform intialization code has registered a console. Platforms using this implementation need to ensure that all console drivers they use that have the CRASH flag set support this (i.e. are written in assembly and comply to the register clobber requirements of plat_crash_console_putc()."
Change-Id: I314cacbcb0bfcc85fe734882e38718f2763cdbf4 Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
e7644eb6 |
| 04-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration
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| #
8e31faa0 |
| 30-Jun-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_handoff_changes" into integration
* changes: chore(xilinx): update warning message feat(versal-net): add cluster check in handoff parameters feat(versal-net): ge
Merge changes from topic "xlnx_handoff_changes" into integration
* changes: chore(xilinx): update warning message feat(versal-net): add cluster check in handoff parameters feat(versal-net): get the handoff params using IPI chore(xilinx): replace fsbl with xbl
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| #
b9d26cd3 |
| 08-Jun-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
chore(xilinx): replace fsbl with xbl
The handoff functionality is common between platforms and all platforms do not use fsbl terminology. Renaming handoff related code to generic naming.
Signed-off
chore(xilinx): replace fsbl with xbl
The handoff functionality is common between platforms and all platforms do not use fsbl terminology. Renaming handoff related code to generic naming.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Change-Id: Ic250af927f33c4fecbc2e6bab01b83a6dd2aab52 Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| #
01a326ab |
| 22-Jun-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
chore(xilinx): reorder include files as per TF-A guidelines
This commit reorders the include files in accordance with the guidelines provided by Trusted Firmware-A (TF-A). The include files are rear
chore(xilinx): reorder include files as per TF-A guidelines
This commit reorders the include files in accordance with the guidelines provided by Trusted Firmware-A (TF-A). The include files are rearranged to ensure a consistent and organized structure in the codebase, facilitating better readability and maintainability.
https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/
For example, to run header check: /tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b
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| #
f51bbacf |
| 12-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(zynqmp): fix prepare_dtb() memory description" into integration
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| #
f1a32f49 |
| 07-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "chore(xilinx): replace ATF with TFA" into integration
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| #
3efee73d |
| 02-Jun-2023 |
Michal Simek <michal.simek@amd.com> |
fix(zynqmp): fix prepare_dtb() memory description
The commit 8ce2fbffe37d ("fix(zynqmp): fix BLXX memory limits for user defined values") fixed logic around BL31_LIMIT but didn't update prepare_dtb(
fix(zynqmp): fix prepare_dtb() memory description
The commit 8ce2fbffe37d ("fix(zynqmp): fix BLXX memory limits for user defined values") fixed logic around BL31_LIMIT but didn't update prepare_dtb() which is also using +1 logic.
Change-Id: Ia6de10d992a552ca9cfa39c14261b0f94cda95ec Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| #
c8be2240 |
| 26-Apr-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
chore(xilinx): replace ATF with TFA
Since the Arm Trusted Firmware(ATF) has been renamed to Trusted Firmware-A (TF-A), replace all the instances of ATF from code comments, macros, variables and func
chore(xilinx): replace ATF with TFA
Since the Arm Trusted Firmware(ATF) has been renamed to Trusted Firmware-A (TF-A), replace all the instances of ATF from code comments, macros, variables and functions to TF-A.
Change-Id: Iab448d96158612a3effb4e49943f8d6cb43aaad5 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| #
c0d8ee38 |
| 26-May-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(zynqmp): handling of type el3 interrrupts" into integration
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| #
e8d61f7d |
| 11-May-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(zynqmp): handling of type el3 interrrupts
The array type_el3_interrupt_table is defined for MAX_INTR_EL3(128) elements and only two interrupts - ARM_IRQ_SEC_SGI_7(15), IRQ_TTC3_1(77) are being h
fix(zynqmp): handling of type el3 interrrupts
The array type_el3_interrupt_table is defined for MAX_INTR_EL3(128) elements and only two interrupts - ARM_IRQ_SEC_SGI_7(15), IRQ_TTC3_1(77) are being handled. Current implementation is consuming 1024 bytes which can be optimized for the number of interrupts to be handled. The current array is replaced with the array of struct zynmp_intr_info_type_el3_t (id and handler as member) and with maximum number of interrupts to be handled as the size of array (MAX_INTR_EL3 = 2). User is expected to adjust MAX_INTR_EL3 based on how many interrupts are handled in TF-A. With the updated implementation, a reduction of 960 bytes is observed. Versal and Versal NET are using similar implementation introduced by commit e497421d7f1e ("feat(versal): add infrastructure to handle multiple interrupts") and commit 0654ab7f7544 ("feat(versal-net): add support for platform management").
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Change-Id: I07aa388d38ac3ff3c0d25decbe0719087b27ee18
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| #
b39af24f |
| 27-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "style(xilinx): fix AMD copyright format" into integration
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| #
ac72bdc0 |
| 20-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
style(xilinx): fix AMD copyright format
There is missing comma in copyright line. It is better to have all Copyrights align to the same style that's why fix it.
Change-Id: Ifc04b474e1a172a7243b073d
style(xilinx): fix AMD copyright format
There is missing comma in copyright line. It is better to have all Copyrights align to the same style that's why fix it.
Change-Id: Ifc04b474e1a172a7243b073d944007cf17d76e87 Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
0aab76a4 |
| 24-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "versal/xlat-v2" into integration
* changes: feat(versal): switch to xlat_v2 fix(xilinx): remove asserts around arg0/arg1
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| #
d84171b4 |
| 20-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "style(xilinx): replace ARM by Arm in copyrights" into integration
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| #
8be20446 |
| 17-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
fix(xilinx): remove asserts around arg0/arg1
The commit a6f340fe58b9 ("Introduce the new BL handover interface") extended handoff to 4 registers instead of 2. Arguments arg0-3 are not used by platfo
fix(xilinx): remove asserts around arg0/arg1
The commit a6f340fe58b9 ("Introduce the new BL handover interface") extended handoff to 4 registers instead of 2. Arguments arg0-3 are not used by platform code but in future they can be used for it. But it doesn't make sense to checking their unused value.
Change-Id: I151e4b1574465409424453c054d937487086b79a Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
619bc13e |
| 14-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix") is enforcing proper case for ARM. That's why fix it in plat/xilinx to make sure
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix") is enforcing proper case for ARM. That's why fix it in plat/xilinx to make sure that pre-commit.copyright won't be touching platform specific files.
Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416 Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
ebb0838a |
| 11-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): add hooks for custom runtime setup" into integration
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| #
88a8938e |
| 06-Apr-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(zynqmp): add hooks for custom runtime setup
Add runtime setup hooks (via custom_runtime_setup()) for low level operations related to setting up the system to correct state.
Change-Id: I4af7050
feat(zynqmp): add hooks for custom runtime setup
Add runtime setup hooks (via custom_runtime_setup()) for low level operations related to setting up the system to correct state.
Change-Id: I4af7050dba2ee2446366d482bef5f5c5dde4bddf Signed-off-by: Amit Nagal <amit.nagal@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| #
d94a7119 |
| 27-Mar-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_zynqmp_changes" into integration
* changes: feat(zynqmp): build pm code as library chore(zynqmp): print entry address to Secure and NS world
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