| #
079c6e24 |
| 08-May-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal): add support for SMCC ARCH SOC ID
Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the
feat(versal): add support for SMCC ARCH SOC ID
Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.
Change-Id: I1466a9ad1bc8dde1cda516ddd3edbaa6a5941237
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
show more ...
|
| #
b2258ce3 |
| 25-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
feat(xilinx): move IPI related macros to plat_ipi.h
The reason is to have all IPI related macros in the same file.
Change-Id: I88ddaa3a5dd1f10114371fc5405f8daf148ca3b8
Signed-off-by: Michal Simek <
feat(xilinx): move IPI related macros to plat_ipi.h
The reason is to have all IPI related macros in the same file.
Change-Id: I88ddaa3a5dd1f10114371fc5405f8daf148ca3b8
Signed-off-by: Michal Simek <michal.simek@amd.com>
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|
| #
d84171b4 |
| 20-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "style(xilinx): replace ARM by Arm in copyrights" into integration
|
| #
114495b5 |
| 17-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(versal): replace FPD_MAINCCI* macros" into integration
|
| #
619bc13e |
| 14-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.
Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>
show more ...
|
| #
245d30ef |
| 14-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
fix(versal): replace FPD_MAINCCI* macros
Replace FPD_MAINCCI* macros by PLAT_ARM_CCI* not to have two different
names for the same IP.
Change-Id: Ia1930e150a51603471051acec5c79c649d57f92f
Signed-of
fix(versal): replace FPD_MAINCCI* macros
Replace FPD_MAINCCI* macros by PLAT_ARM_CCI* not to have two different
names for the same IP.
Change-Id: Ia1930e150a51603471051acec5c79c649d57f92f
Signed-off-by: Michal Simek <michal.simek@amd.com>
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|
| #
8c56a6ba |
| 16-Feb-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "versal-ipi" into integration
* changes:
fix(versal): fix incorrect regbase for PMC IPI
fix(versal): sync location based on IPI_ID macros
fix(xilinx): remove unused ma
Merge changes from topic "versal-ipi" into integration
* changes:
fix(versal): fix incorrect regbase for PMC IPI
fix(versal): sync location based on IPI_ID macros
fix(xilinx): remove unused mailbox macros
show more ...
|
| #
c4185d51 |
| 09-Feb-2023 |
Michal Simek <michal.simek@amd.com> |
fix(versal): fix incorrect regbase for PMC IPI
PMC ipi register base can't be the same as is for IPI_ID_APU that's why
that address is not correct and needs to be fixed.
Change-Id: I7ff2c9c0dd59954
fix(versal): fix incorrect regbase for PMC IPI
PMC ipi register base can't be the same as is for IPI_ID_APU that's why
that address is not correct and needs to be fixed.
Change-Id: I7ff2c9c0dd5995487e41f6b1060e4c9880c009fa
Signed-off-by: Michal Simek <michal.simek@amd.com>
show more ...
|
| #
207bda95 |
| 13-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes Id49d94f6,I35316310 into integration
* changes:
feat(versal): add infrastructure to handle multiple interrupts
fix(versal): add SGI register call version check
|
| #
e497421d |
| 26-Aug-2022 |
Tanmay Shah <tanmay.shah@amd.com> |
feat(versal): add infrastructure to handle multiple interrupts
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infras
feat(versal): add infrastructure to handle multiple interrupts
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
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|
| #
8b06f0a2 |
| 28-Jul-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(xilinx): miscellaneous fixes for xilinx platforms" into integration
|
| #
bfc514f1 |
| 28-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(xilinx): miscellaneous fixes for xilinx platforms
This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.
Signed-off-by: Michal S
fix(xilinx): miscellaneous fixes for xilinx platforms
This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4cdb89ffec7d5abc64e065ed5b5e5d10b30ab9f9
show more ...
|
| #
1ee0eef9 |
| 25-Jul-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(versal): remove clock related macros" into integration
|
| #
47f81453 |
| 21-Jul-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): remove clock related macros
TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also p
fix(versal): remove clock related macros
TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also previous phase can disable access to these registers that's
why better to remove them.
Change-Id: I53ba344ad932c532b0babdce9d2b26e4c2c1b846
Signed-off-by: Michal Simek <michal.simek@amd.com>
show more ...
|
| #
0d9133d4 |
| 02-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(xilinx): add SPP/EMU platform support for versal" into integration
|
| #
be73459a |
| 13-Apr-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(xilinx): add SPP/EMU platform support for versal
This patch adds SPP/EMU platform support for Xilinx Versal and
also updating the documentation.
Signed-off-by: Venkatesh Yadav Abbarapu <venkat
feat(xilinx): add SPP/EMU platform support for versal
This patch adds SPP/EMU platform support for Xilinx Versal and
also updating the documentation.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ibdadec4d00cd33ea32332299e7a00de31dc9d60b
show more ...
|
| #
29ad12a7 |
| 01-Dec-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration
* changes:
fix(plat/xilinx/versal): resolve misra R10.6
fix(plat/xilinx/versal): resolve misra R14.4
fix(p
Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration
* changes:
fix(plat/xilinx/versal): resolve misra R10.6
fix(plat/xilinx/versal): resolve misra R14.4
fix(plat/xilinx/versal): resolve misra R17.7
fix(plat/xilinx/versal): resolve misra R10.3
fix(plat/xilinx/versal): resolve misra R7.2
fix(plat/xilinx/versal): resolve misra R15.7
fix(plat/xilinx/versal): resolve misra R15.6
fix(plat/xilinx/versal): resolve misra R10.1 in pm services
fix(plat/xilinx/versal): resolve misra R20.7 in pm services
fix(plat/xilinx/versal): resolve misra R10.3 in pm services
fix(plat/xilinx/versal): resolve misra R10.6 in pm services
fix(plat/xilinx/versal): resolve misra R16.3 in pm services
fix(plat/xilinx/versal): resolve misra R15.6 in pm services
show more ...
|
| #
b2bb3efb |
| 13-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R10.3
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or of a different e
fix(plat/xilinx/versal): resolve misra R10.3
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I9c6dd8dba40db8067b46947ceff295732648612a
show more ...
|
| #
0623dcea |
| 11-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R7.2
MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
represented in an unsigned type
Signed-off
fix(plat/xilinx/versal): resolve misra R7.2
MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
represented in an unsigned type
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iaf6db75e42913ddceccb803426287d0c47d7f31d
show more ...
|
| #
5d1c211e |
| 05-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R10.3 in pm services
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or o
fix(plat/xilinx/versal): resolve misra R10.3 in pm services
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I73c056ff4df2f14e04c92a49ac5c97e578e82107
show more ...
|
| #
511c7f3a |
| 13-Apr-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "dcc_console" into integration
* changes:
plat:xilinx:versal: Add JTAG DCC support
plat:xilinx:zynqmp: Add JTAG DCC support
drivers: dcc: Support JTAG DCC console
|
| #
0b25f404 |
| 27-Nov-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Mic
plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
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|
| #
8eceb1c9 |
| 31-Mar-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "Create separate header for ARM specific SMCCC defines" into integration
|
| #
53adebad |
| 27-Mar-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
Create separate header for ARM specific SMCCC defines
Moved SMCCC defines from plat_arm.h to new <smccc_def.h> header
and include this header in all ARM platforms.
Signed-off-by: Manish V Badarkhe
Create separate header for ARM specific SMCCC defines
Moved SMCCC defines from plat_arm.h to new <smccc_def.h> header
and include this header in all ARM platforms.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I4cbc69c7b9307461de87b7c7bf200dd9b810e485
show more ...
|
| #
208ebe7c |
| 23-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "xilinx: versal: PLM to ATF handover" into integration
|