| 89ea53c7 | 04-May-2018 |
Andrew F. Davis <afd@ti.com> |
ti: k3: drivers: ti_sci: Add support for Processor control
TI-SCI message protocol provides support for controlling of various
physical cores available in the SoC. In order to control which host is
ti: k3: drivers: ti_sci: Add support for Processor control
TI-SCI message protocol provides support for controlling of various
physical cores available in the SoC. In order to control which host is
capable of controlling a physical processor core, there is a processor
access control list that needs to be populated as part of the board
configuration data.
Introduce support for the set of TI-SCI message protocol APIs that
provide us with this capability of controlling physical cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
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| 7b8f3e2d | 04-May-2018 |
Andrew F. Davis <afd@ti.com> |
ti: k3: drivers: ti_sci: Add support for Core control
Since system controller now has control over SoC power management, core
operation such as reset need to be explicitly requested to reboot the So
ti: k3: drivers: ti_sci: Add support for Core control
Since system controller now has control over SoC power management, core
operation such as reset need to be explicitly requested to reboot the SoC.
Add support for this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
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| 6d1dfef6 | 04-May-2018 |
Andrew F. Davis <afd@ti.com> |
ti: k3: drivers: ti_sci: Add support for Clock control
TI-SCI message protocol provides support for management of various
hardware entities within the SoC.
In general, we expect to function at a de
ti: k3: drivers: ti_sci: Add support for Clock control
TI-SCI message protocol provides support for management of various
hardware entities within the SoC.
In general, we expect to function at a device level of abstraction,
however, for proper operation of hardware blocks, many clocks directly
supplying the hardware block needs to be queried or configured.
Introduce support for the set of TI-SCI message protocol support that
provide us with this capability.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
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| 3858452d | 04-May-2018 |
Andrew F. Davis <afd@ti.com> |
ti: k3: drivers: ti_sci: Add support for Device control
TI-SCI message protocol provides support for management of various
hardware entitites within the SoC.
We introduce the fundamental device man
ti: k3: drivers: ti_sci: Add support for Device control
TI-SCI message protocol provides support for management of various
hardware entitites within the SoC.
We introduce the fundamental device management capability support to
the driver protocol as part of this change.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
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| deed2b83 | 25-Jun-2018 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Enable interrupts before entering standby state
To wake a core from wfi interrupts must be enabled, in some cases they
may not be and so we can lock up here. Unconditionally enable i
ti: k3: common: Enable interrupts before entering standby state
To wake a core from wfi interrupts must be enabled, in some cases they
may not be and so we can lock up here. Unconditionally enable interrupts
before wfi and then restore interrupt state.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| 2e9c9e82 | 14-Oct-2016 |
Benjamin Fair <b-fair@ti.com> |
ti: k3: common: Add PSCI stubs
These functions are used for the PSCI implementation and are needed to
build BL31, but we cannot implement them until we add several more drivers
related to ti-sci so
ti: k3: common: Add PSCI stubs
These functions are used for the PSCI implementation and are needed to
build BL31, but we cannot implement them until we add several more drivers
related to ti-sci so these are only stubs for now.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| e9cb89cf | 14-Oct-2016 |
Nishanth Menon <nm@ti.com> |
ti: k3: common: Program A53 arch timer frequency
Provide K3_TIMER_FREQUENCY for the platform configuration if the GTC
clock is selected statically and override option if the platform has a
different
ti: k3: common: Program A53 arch timer frequency
Provide K3_TIMER_FREQUENCY for the platform configuration if the GTC
clock is selected statically and override option if the platform has a
different configuration.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
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| e67bfcf3 | 14-Oct-2016 |
Nishanth Menon <nm@ti.com> |
ti: k3: common: Enable MMU using xlat_tables_v2 library
This library will be used to properly set up mappings from different
bootloaders at different exception levels. It ensures that memory mapped
ti: k3: common: Enable MMU using xlat_tables_v2 library
This library will be used to properly set up mappings from different
bootloaders at different exception levels. It ensures that memory mapped
devices such as UARTs are still accessible and memory regions have the
correct access permissions.
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| 878bd5ce | 14-Oct-2016 |
Benjamin Fair <b-fair@ti.com> |
ti: k3: common: Implement topology functions
These functions describe the layout of the cores and clusters in order to
support the PSCI framework.
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signe
ti: k3: common: Implement topology functions
These functions describe the layout of the cores and clusters in order to
support the PSCI framework.
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| a546d25b | 14-Oct-2016 |
Benjamin Fair <b-fair@ti.com> |
ti: k3: common: Populate BL32 and BL33 entrypoint
Because there is no BL2, BL31 must determine the entrypoint and memory
location of BL32 and BL33 on its own.
BL32_BASE and PRELOADED_BL33_BASE will
ti: k3: common: Populate BL32 and BL33 entrypoint
Because there is no BL2, BL31 must determine the entrypoint and memory
location of BL32 and BL33 on its own.
BL32_BASE and PRELOADED_BL33_BASE will be set in the corresponding board
makefile. We also allow a DTB address to be specified for cases when BL33
is a Linux image.
NOTE: It is possible to pull in this information from device tree as
well, however libfdt does not contain the required hooks to make this
happen at this point in time.
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| 89574715 | 18-Oct-2016 |
Benjamin Fair <b-fair@ti.com> |
ti: k3: common: Add platform core management helpers
The K3 family of SoCs has multiple interconnects. The key interconnect
for high performance processors is the MSMC3 interconnect. This is
an io-c
ti: k3: common: Add platform core management helpers
The K3 family of SoCs has multiple interconnects. The key interconnect
for high performance processors is the MSMC3 interconnect. This is
an io-coherent interconnect which exports multiple ports for each
processor cluster.
Sometimes, port 0 of the MSMC may not have an ARM cluster OR is isolated
such that the instance of ATF does not manage it. Define macros
in platform_def.h to help handle this.
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
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