Merge pull request #1914 from marex/arm/master/d3draak-v2.0.1

Arm/master/d3draak v2.0.1

rcar_gen3: plat: Add initial D3 support

Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code
will be added separately.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Merge pull request #1854 from marex/arm/master/atf-v2.0.1

Arm/master/atf v2.0.1

rcar_gen3: Add M3-W 3.0 support

Add support for the M3W 3.0 SoC and synchronize the upstream ATF with
Renesas downstream ATF release v2.0.1.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.co

rcar_gen3: Add M3-W 3.0 support

Add support for the M3W 3.0 SoC and synchronize the upstream ATF with
Renesas downstream ATF release v2.0.1.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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Merge pull request #1833 from marex/arm/master/pci-v2.0.0

rcar_gen3: plat: Prevent PCIe hang during L1X config access

rcar_gen3: plat: Prevent PCIe hang during L1X config access

In case the PCIe controller receives a L1_Enter_PM DLLP, it will
disable the internal PLLs. The system software cannot predict it
and can

rcar_gen3: plat: Prevent PCIe hang during L1X config access

In case the PCIe controller receives a L1_Enter_PM DLLP, it will
disable the internal PLLs. The system software cannot predict it
and can attempt to perform device config space access across the
PCIe link while the controller is in this transitional state. If
such condition happens, the PCIe controller register access will
trigger ARM64 SError exception.

This patch adds checks for which PCIe controller is enabled,
checks whether the PCIe controller is in such a transitional
state and if so, first completes the transition and then restarts
the instruction which caused the SError.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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Merge pull request #1804 from antonio-nino-diaz-arm/an/cleanup

Minor cleanup

Remove unneeded include paths in PLAT_INCLUDES

Also, update platform_def.h guidelines about includes in the porting
guide.

Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3
Signed-off-by: Antoni

Remove unneeded include paths in PLAT_INCLUDES

Also, update platform_def.h guidelines about includes in the porting
guide.

Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1793 from marex/arm/master/fixes-v2.0.0

Arm/master/fixes v2.0.0

Revert "rcar_gen3: plat: Enable programmable CPU reset address"

This reverts commit d48536e2f92d47ebb92cf12b35133c3be2d0e459,
which misbehaves on R-Car H3 ES2.0. Until the reason for that
misbehavio

Revert "rcar_gen3: plat: Enable programmable CPU reset address"

This reverts commit d48536e2f92d47ebb92cf12b35133c3be2d0e459,
which misbehaves on R-Car H3 ES2.0. Until the reason for that
misbehavior is understood, revert the commit.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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Merge pull request #1734 from marex/arm/master/update-rcar-2.0.0

Arm/master/update rcar 2.0.0

rcar_gen3: drivers: pwrc: Switch to common delay implementation

Replace the ad-hoc implementation of delay in PWRC driver
with common R-Car delay code.

Signed-off-by: Marek Vasut <marek.vasut+renes

rcar_gen3: drivers: pwrc: Switch to common delay implementation

Replace the ad-hoc implementation of delay in PWRC driver
with common R-Car delay code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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rcar_gen3: drivers: delay: Rewrite from assembler to C

Rewrite the delay code from assembler to C.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: drivers: cpld: Move rcar_cpld_reset_cpu() into header

Move the rcar_cpld_reset_cpu() function into header file and zap the externs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.

rcar_gen3: drivers: cpld: Move rcar_cpld_reset_cpu() into header

Move the rcar_cpld_reset_cpu() function into header file and zap the externs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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rcar_gen3: plat: Enable programmable CPU reset address

The reset address is programmable on the R-Car Gen3, enable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Disable SVE

Apply 3872fc2d1fc5 ("Do not enable SVE on pre-v8.2 platforms") to
R-Car Gen3 too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Add missing dependency to rcar_srecord

Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord
target, which uses those ELF files to generate the SRECs.

Signed-off

rcar_gen3: plat: Add missing dependency to rcar_srecord

Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord
target, which uses those ELF files to generate the SRECs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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Merge pull request #1704 from marex/arm/master/memsize-passing-v1

Arm/master/memsize passing v1

plat: rcar: Pass DTB with DRAM layout from BL2 to next stages

Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so
that the BL33 can simply consume it and get accurate DRAM layout in

plat: rcar: Pass DTB with DRAM layout from BL2 to next stages

Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so
that the BL33 can simply consume it and get accurate DRAM layout info.
BL33 is in most usecases U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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Merge pull request #1687 from ldts/rcar_gen3/maintain_4

rcar-gen3: lock RPC hyper-flash access

rcar-gen3: control RPC hyper-flash access

RCAR_RPC_HYPERFLASH_LOCKED can be set to 0 as a build option if the
user needs to allow u-boot to reprogram the ATF firmware using a FIP
image (as a faster

rcar-gen3: control RPC hyper-flash access

RCAR_RPC_HYPERFLASH_LOCKED can be set to 0 as a build option if the
user needs to allow u-boot to reprogram the ATF firmware using a FIP
image (as a faster alternative of toggling numerous DIP switches on
the board and using ascii-xfer of srec files)

The code being controlled with this commit should only be re-enabled for
debugging (_never_ on a product release)

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>

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Merge pull request #1582 from ldts/rcar_gen3/upstream

rcar_gen3: initial support

rcar_gen3: drivers: staging

- ddr
- pfc [pin function controller]
- qos [bandwidth]

checkpatch.pl is generating too many errors.

rcar-gen3: initial commit for the rcar-gen3 boards

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author

rcar-gen3: initial commit for the rcar-gen3 boards

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date: Thu Aug 30 21:26:41 2018 +0900
Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
git@github.com:ARMmbed/mbedtls.git [devel]

Merge: 68dbc94 f34a4c1
Author: Simon Butcher <simon.butcher@arm.com>
Date: Thu Aug 30 00:57:28 2018 +0100

* optee_os:
https://github.com/BayLibre/optee_os

Until it gets merged into OP-TEE, the port requires Renesas' Trusted
Environment with a modification to support power management.

Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
Date: Thu Aug 30 16:49:49 2018 +0200
plat-rcar: cpu-suspend: handle the power level
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
The port has beent tested using mainline uboot.

Author: Fabio Estevam <festevam@gmail.com>
Date: Tue Sep 4 10:23:12 2018 -0300

*linux:
The port has beent tested using mainline kernel.

Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Sep 16 11:52:37 2018 -0700
Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
-------
enable kernel's cpuidle arm_idle driver and boot

* system suspend
--------------
$ cat suspend.sh
#!/bin/bash
i2cset -f -y 7 0x30 0x20 0x0F
read -p "Switch off SW23 and press return " foo
echo mem > /sys/power/state

* cpu hotplug:
------------
$ cat offline.sh
#!/bin/bash
nbr=$1
echo 0 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

$ cat online.sh
#!/bin/bash
nbr=$1
echo 1 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

Signed-off-by: ldts <jramirez@baylibre.com>

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