Merge "fix(qemu-sbsa): enable FGT" into integration

fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <mar

fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238

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Merge changes from topic "jc/sve" into integration

* changes:
fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld
fix(tc): enable dynamic feature detection of FEAT_SVE for No

Merge changes from topic "jc/sve" into integration

* changes:
fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld
fix(tc): enable dynamic feature detection of FEAT_SVE for NormalWorld

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fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2:

fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2: FEAT_STATE_CHECK ( for configurable platforms)
to meet the feature detection requirements dynamically, mainly
targetting configurable/Fixed Virtual platforms.

With this mechanism in place, we are refactoring all the existing
feature flags to the FEAT_STATE_CHECK option(=2), including
FEAT_SVE explicitly for FVPs.

SVE Patch Reference:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19888/25

This newly introduced change, breaks the existing behaviour especially
for virtual platforms, who have set the ENABLE_SVE_FOR_NS flag to 1.

Moving ahead, we advise the platforms to take the following steps while
enabling the features:

1. If the platform is configurable (virtual), and want to ensure feature
detection happens dynamically at runtime, set the build flags to
FEAT_STATE_CHECK(=2).

2. For real(fixed) platforms, depending on the features supported by the
hardware and platform wants to enable it, platforms could set build
flags to FEAT_STATE_ALWAYS(=1).

(Note: Only the non-secure world enablement related build flags have
been refactored to take the values within 0 to 2. As earlier Secure
world enablement flags will still remain boolean.)

Henceforth, in order to keep it aligned with this tri-state mechanism,
changing the qemu platform default to the now supported dynamic
option(=2), so the right decision can be made by the code at runtime.

Change-Id: Icc95b8b872378b7874d4345b631adfc314e4dada
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topics "qemu", "qemu_sbsa" into integration

* changes:
feat(qemu): add A76/N1 cpu support for virt
feat(qemu): add "neoverse-n1" cpu support
feat(qemu): make coherent memory

Merge changes from topics "qemu", "qemu_sbsa" into integration

* changes:
feat(qemu): add A76/N1 cpu support for virt
feat(qemu): add "neoverse-n1" cpu support
feat(qemu): make coherent memory section optional
refactor(qemu): make use of setup_page_tables()

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feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c7111

feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f

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Merge "fix(qemu-sbsa): enable SVE and SME" into integration

fix(qemu-sbsa): enable SVE and SME

Commit 337ff4f1dd6604738d79fd3fa275ae74d74256b2 enabled SVE/SME for
qemu platform. Let do the same for qemu-sbsa one too.

With this change I can boot Debian 'book

fix(qemu-sbsa): enable SVE and SME

Commit 337ff4f1dd6604738d79fd3fa275ae74d74256b2 enabled SVE/SME for
qemu platform. Let do the same for qemu-sbsa one too.

With this change I can boot Debian 'bookworm' installed using Max cpu.

Info from referenced commit:

Starting with QEMU v3.1.0 (Dec 2018), QEMU's TCG emulation engine supports
the SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained
SME support.

As it stands today, running TF-A under QEMU with "-cpu max" makes Linux
hang, because SME and SVE accesses trap to EL3, but are never handled
there. This is because the Linux kernel sees the SVE or SME feature bits,
and assumes firmware has enabled the feature for lower exception levels.
This requirement is described in the Linux kernel booting protocol.

Enable those features in the TF-A build, so that BL31 does the proper
EL3 setup to make the feature usable in non-secure world.
We check the actual feature bits before accessing SVE or SME registers,
so this is safe even for older QEMU version or when not running with
-cpu max. As SVE and SME are AArch64 features only, do not enable them
when building for AArch32.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9ea1f91e6b801218d944e8a7d798d5ae568ed59a

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Merge changes from topic "ck/mpmm" into integration

* changes:
docs(maintainers): add Chris Kay to AMU and MPMM
feat(tc): enable MPMM
feat(mpmm): add support for MPMM
feat(amu): enable per-c

Merge changes from topic "ck/mpmm" into integration

* changes:
docs(maintainers): add Chris Kay to AMU and MPMM
feat(tc): enable MPMM
feat(mpmm): add support for MPMM
feat(amu): enable per-core AMU auxiliary counters
docs(amu): add AMU documentation
refactor(amu): refactor enablement and context switching
refactor(amu): detect auxiliary counters at runtime
refactor(amu): detect architected counters at runtime
refactor(amu): conditionally compile auxiliary counter support
refactor(amu): factor out register accesses
refactor(amu)!: privatize unused AMU APIs
refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK`
build(amu): introduce `amu.mk`
build(fconf)!: clean up source collection
feat(fdt-wrappers): add CPU enumeration utility function
build(fdt-wrappers): introduce FDT wrappers makefile
build(bl2): deduplicate sources
build(bl1): deduplicate sources

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build(fdt-wrappers): introduce FDT wrappers makefile

This has been introduced to simplify dependencies on the FDT wrappers.
We generally want to avoid pulling in components on a file-by-file
basis,

build(fdt-wrappers): introduce FDT wrappers makefile

This has been introduced to simplify dependencies on the FDT wrappers.
We generally want to avoid pulling in components on a file-by-file
basis, particularly as we are trying to draw conceptual boxes around
components in preparation for transitioning the build system to CMake,
where dependencies are modelled on libraries rather than files.

Signed-off-by: Chris Kay <chris.kay@arm.com>
Change-Id: Idb7ee05a9b54a8caa3e07f36e608867e20b6dcd5

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Merge changes I36e45c0a,I69c21293 into integration

* changes:
plat/qemu: add "max" cpu support
Add support for QEMU "max" CPU

plat/qemu: add "max" cpu support

Add support to qemu "max" cpu for both "qemu" ('virt') and
"qemu_sbsa" ('sbsa-ref') platforms.

Change-Id: I36e45c0a3c4e30ba546d2a3cb44dfef11a680305
Signed-off-by: L

plat/qemu: add "max" cpu support

Add support to qemu "max" cpu for both "qemu" ('virt') and
"qemu_sbsa" ('sbsa-ref') platforms.

Change-Id: I36e45c0a3c4e30ba546d2a3cb44dfef11a680305
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

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Merge changes from topic "qemu-sbsa-topology-psci" into integration

* changes:
qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller
qemu/qemu_sbsa: topology is different from qemu so add

Merge changes from topic "qemu-sbsa-topology-psci" into integration

* changes:
qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller
qemu/qemu_sbsa: topology is different from qemu so add handling
qemu/common : change DEVICE2 definition for MMU
qemu/aarch64/plat_helpers.S : calculate the position shift

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qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific ver

qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific version of PSCI functions for the
platform. Also adjusted the MMU range to also include the new EC.

Add a new MMU region for the embedded controller and increase the
size of xlat tables by one for the new region.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee

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qemu/qemu_sbsa: topology is different from qemu so add handling

sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topolog

qemu/qemu_sbsa: topology is different from qemu so add handling

sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topology file
and increase the BL31_SIZE to accommodate the bigger table sizes. Change
platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so
plat_helpers.S calculates correct result.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7

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Merge "qemu/qemu_sbsa: enable secure variable storage" into integration

qemu/qemu_sbsa: enable secure variable storage

This implements support for UEFI secure variable storage
using standalone MM framework on qemu_sbsa platform.

Non-secure shared memory between UEFI an

qemu/qemu_sbsa: enable secure variable storage

This implements support for UEFI secure variable storage
using standalone MM framework on qemu_sbsa platform.

Non-secure shared memory between UEFI and standalone MM
is allocated at the top of DRAM.
DRAM size of qemu_sbsa varies depends on the QEMU parameter,
so the non-secure shared memory is allocated by trusted firmware
and passed the base address and size to UEFI through device tree
"/reserved-memory" node.

Change-Id: I367191f408eb9850b7ec7761ee346b014c539767
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>

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Merge "plat/qemu_sbsa: Include libraries for Cortex-A72" into integration

plat/qemu_sbsa: Include libraries for Cortex-A72

Include libraries needed to emulate Cortex-A72 on
sbsa-ref target of QEMU.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Change-Id: I98c

plat/qemu_sbsa: Include libraries for Cortex-A72

Include libraries needed to emulate Cortex-A72 on
sbsa-ref target of QEMU.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Change-Id: I98cf17b1662c70898977a841af07e07b5cfca8ba

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Merge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integration

plat/qemu_sbsa: Remove cortex_a53 and aem_generic

The qemu_sbsa platform uses 42bit address size but
the cortex-a53 only supports 40bit addressing, the
cpu is incompatible with the platform.

The ae

plat/qemu_sbsa: Remove cortex_a53 and aem_generic

The qemu_sbsa platform uses 42bit address size but
the cortex-a53 only supports 40bit addressing, the
cpu is incompatible with the platform.

The aem_generic is also not used with qemu_sbsa, in
fact, the platform currently only properly supports
the cortex-a57 cpu.

Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14
Signed-off-by: Tomas Pilar <tomas@nuviateam.com>

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Merge "qemu/qemu_sbsa: enable SPM support" into integration

qemu/qemu_sbsa: enable SPM support

Enable the spm_mm framework for the qemu_sbsa platform.
Memory layout required for spm_mm is created in secure SRAM.

Co-developed-by: Fu Wei <fu.wei@linaro.org>
S

qemu/qemu_sbsa: enable SPM support

Enable the spm_mm framework for the qemu_sbsa platform.
Memory layout required for spm_mm is created in secure SRAM.

Co-developed-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a

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Merge "TF-A GICv3 driver: Introduce makefile" into integration

TF-A GICv3 driver: Introduce makefile

This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affectin

TF-A GICv3 driver: Introduce makefile

This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.
The patch adds GICv3 driver configuration flags
'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and
'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in
'GICv3 driver options' section of 'build-option.rst'
document.

NOTE: Platforms with GICv3 driver need to be modified to
include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.

Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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