Tegra194: remove GPU, MPCORE and PTC registers from streamid list

GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.

Change-Id: I14b450a11f02ad6c1a9

Tegra194: remove GPU, MPCORE and PTC registers from streamid list

GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.

Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: Support SMC64 encoding for MCE calls

This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.

Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-of

Tegra194: Support SMC64 encoding for MCE calls

This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.

Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: Enable MCE driver

This patch enable MCE driver for T19x SoC. The MCE driver
takes care of the communication with the MCE firmware to
achieve:

- Cold boot
- Warm boot
- Core/Cluster/System

Tegra194: Enable MCE driver

This patch enable MCE driver for T19x SoC. The MCE driver
takes care of the communication with the MCE firmware to
achieve:

- Cold boot
- Warm boot
- Core/Cluster/System Power management
- Custom MCE requests

Change-Id: I75854c0b649a691e9b244d9ed9fc1c19743e3e8d
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: enable SMMU

Enable smmu by setting ENABLE_SMMU_DEVICE to 1.

Change-Id: I9135071b257a166fa6082b7fe409bcd315cf6838
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: add support for multiple SMMU devices

This patch adds support for all three SMMU devices present on the SoC.

The following changes have been done:
Add SMMU devices to the memory map

Tegra194: add support for multiple SMMU devices

This patch adds support for all three SMMU devices present on the SoC.

The following changes have been done:
Add SMMU devices to the memory map
Update register read and write functions

Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: add SMMU and mc_sid support

Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to

Tegra194: add SMMU and mc_sid support

Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to hold register values during suspend.

Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: psci: support for 64-bit TZDRAM base

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: I3c18eb844963f39f91b5ac45e3709f335

Tegra194: psci: support for 64-bit TZDRAM base

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: base commit for the platform

This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.

Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Var

Tegra194: base commit for the platform

This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.

Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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