| #
698f4250 |
| 21-Apr-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: smmu: disable TCU prefetch for all the 64 contexts
This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.
Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101
Tegra: smmu: disable TCU prefetch for all the 64 contexts
This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.
Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| #
ddc1c56f |
| 30-Mar-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #875 from vwadekar/tegra186-platform-support-v2
Tegra186 platform support v2
|
| #
68c7de6f |
| 18-Mar-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: save/restore BL31 context to/from TZDRAM
This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we
Tegra186: save/restore BL31 context to/from TZDRAM
This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we need to copy the entire BL31 code to
TZDRAM before entering the state.
In order to restore the state on exiting system suspend, a new
CPU reset handler is implemented which gets copied to TZDRAM
during boot. TO keep things simple we use this same reset handler
for booting secondary CPUs too.
Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| #
891685a5 |
| 23-Mar-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #865 from vwadekar/tegra186-platform-support-v1
Tegra186 platform support v1
|
| #
4122151f |
| 03-Mar-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: smmu: driver for the smmu hardware block
This patch adds a device driver for the SMMU hardware block on
Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on
Tegra186. The driver only
Tegra186: smmu: driver for the smmu hardware block
This patch adds a device driver for the SMMU hardware block on
Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on
Tegra186. The driver only supports saving the SMMU settings
before entering system suspend. The MC driver and the NS world
clients take care of programming their own settings.
Change-Id: Iab5a90310ee10f6bc8745451ce50952ab3de7188
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|