Tegra: remove support for SEPARATE_CODE_AND_RODATA=0

Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.

This patch uses the common macros provided by bl_common.h as a result
and add

Tegra: remove support for SEPARATE_CODE_AND_RODATA=0

Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.

This patch uses the common macros provided by bl_common.h as a result
and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set
to '1'.

Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler

The 'plat_core_pos_by_mpidr' handler gets called very early during boot
and the compiler generated code overwrites the caller's regist

Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler

The 'plat_core_pos_by_mpidr' handler gets called very early during boot
and the compiler generated code overwrites the caller's registers.

This patch converts the 'plat_core_pos_by_mpidr' handler into an assembly
function and uses registers x0-x3, to fix this anomaly.

Change-Id: I8d974e007a0bad039defaf77b11a180d899ead3c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: aarch64: calculate core position from one place

This patch updates 'plat_my_core_pos' handler to call
'plat_core_pos_from_mpidr' instead of implementing the same logic
at two places.

Change-

Tegra: aarch64: calculate core position from one place

This patch updates 'plat_my_core_pos' handler to call
'plat_core_pos_from_mpidr' instead of implementing the same logic
at two places.

Change-Id: I1e56adaa10dc2fe3440e5507e0e260d8932e6657
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra: smmu: export handlers to read/write SMMU registers

This patch exports the SMMU register read/write handlers for platforms.

Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by:

Tegra: smmu: export handlers to read/write SMMU registers

This patch exports the SMMU register read/write handlers for platforms.

Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: remove context save sequence

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS

Tegra: smmu: remove context save sequence

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra: fiq_glue: remove bakery locks from interrupt handler

This patch removes usage of bakery_locks from the FIQ handler, as it
creates unnecessary dependency whenever the watchdog timer interrupt

Tegra: fiq_glue: remove bakery locks from interrupt handler

This patch removes usage of bakery_locks from the FIQ handler, as it
creates unnecessary dependency whenever the watchdog timer interrupt
fires. All operations inside the interrupt handler are 'reads', so
no need for serialization.

Change-Id: I3f675e610e4dabc5b1435fdd24bc28e424f5a8e4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: disable CPUACTLR access from lower exception levels

This patch resets the macros to update the CPUACTLR_ELx to make
them generic for all exception levels.

Change-Id: I33e9b860efb543934b654a2

Tegra: disable CPUACTLR access from lower exception levels

This patch resets the macros to update the CPUACTLR_ELx to make
them generic for all exception levels.

Change-Id: I33e9b860efb543934b654a2f5d775135df7f1aa6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topic "spmd-sel2" into integration

* changes:
SPMD: add command line parameter to run SPM at S-EL2 or S-EL1
SPMD: smc handler qualify secure origin using booleans
SPMD: SPMC

Merge changes from topic "spmd-sel2" into integration

* changes:
SPMD: add command line parameter to run SPM at S-EL2 or S-EL1
SPMD: smc handler qualify secure origin using booleans
SPMD: SPMC init, SMC handler cosmetic changes
SPMD: [tegra] rename el1_sys_regs structure to sys_regs
SPMD: Adds partially supported EL2 registers.
SPMD: save/restore EL2 system registers.

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Tegra: spe: use CONSOLE_T_BASE to save MMIO base address

Commit ac71344e9eca1f7d1e0ce4a67aca776470639b1c moved the base address
for the MMIO aperture of the console inside the console_t struct. As
a

Tegra: spe: use CONSOLE_T_BASE to save MMIO base address

Commit ac71344e9eca1f7d1e0ce4a67aca776470639b1c moved the base address
for the MMIO aperture of the console inside the console_t struct. As
a result, the driver should now save the MMIO base address to console_t
at offset marked by the CONSOLE_T_BASE macro.

This patch updates the SPE console driver to use the CONSOLE_T_BASE macro
to save/access the MMIO base address.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I42afc2608372687832932269108ed642f218fd40

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SPMD: [tegra] rename el1_sys_regs structure to sys_regs

Renamed the structure according to a SPMD refactoring
introduced in <c585d07aa> since this structure is used
to service both EL1 and EL2 as op

SPMD: [tegra] rename el1_sys_regs structure to sys_regs

Renamed the structure according to a SPMD refactoring
introduced in <c585d07aa> since this structure is used
to service both EL1 and EL2 as opposed to serving only EL1.

Change-Id: I23b7c089e53f617157a4b4e6443acce50d85c3b5
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>

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spe: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data struct

spe: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I75dbfafb67849833b3f7b5047e237651e3f553cd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Tegra: spe: uninit console on a timeout

There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmwar

Tegra: spe: uninit console on a timeout

There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmware to respond indefinitely.
The console driver must detect such scenarios and uninit the
interface as a result.

This patch adds a timeout to the interaction with the SPE
firmware and uninits the interface if it times out.

Change-Id: I06f27a858baed25711d41105b4110865f1a01727
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: handler to check support for System Suspend

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the

Tegra: handler to check support for System Suspend

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp_ipc: improve cyclomatic complexity

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

Tegra: bpmp_ipc: improve cyclomatic complexity

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

complexity < 10 is accepted
10 <= complexity < 20 has to be justified
complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'ipc_send_req_atomic'
handler to reduce the McCabe Cyclomatic Complexity for this function

Change-Id: I20fef79a771301e1c824aea72a45ff83f97591d5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: platform handler to relocate BL32 image

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZD

Tegra: platform handler to relocate BL32 image

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.

Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: common: improve cyclomatic complexity

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

co

Tegra: common: improve cyclomatic complexity

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

complexity < 10 is accepted
10 <= complexity < 20 has to be justified
complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'bl31_early_platform_setup'
handler to reduce the McCabe Cyclomatic Complexity for this function.

Change-Id: Ifb628e33269b388f9323639cd97db761a7e049c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: delay_timer: support for physical secure timer

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure tim

Tegra: delay_timer: support for physical secure timer

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.

This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.

Change-Id: I2c00f8cb4c48b25578971c626c314603906ad7cc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp: fix multiple MISRA issues

This patch fixes violations for the following MISRA rules

* Rule 5.7 "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inapp

Tegra: bpmp: fix multiple MISRA issues

This patch fixes violations for the following MISRA rules

* Rule 5.7 "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.3 "The value of an expression shall not be assigned to an object
with a narrower essential type or of a different essential type
category"
* Rule 10.4 "Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category"
* Rule 20.7 "Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses"
* Rule 21.1 "#define and #undef shall not be used on a reserved identifier
or reserved macro name"

Change-Id: I83cbe659c2d72e76dd4759959870b57c58adafdf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: compile PMC driver for Tegra132/Tegra210 platforms

The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platfo

Tegra: compile PMC driver for Tegra132/Tegra210 platforms

The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platform specific makefiles.

As a result, the PMC code from common code has been moved to Tegra132
and Tegra210 platform ports.

Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler

This patch removes the per-platform, weakly defined TZDRAM setup handler,
as all affected platforms implement the actual handler.

Chang

Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler

This patch removes the per-platform, weakly defined TZDRAM setup handler,
as all affected platforms implement the actual handler.

Change-Id: I95d04b2a771bc5d673e56b097d45c493fa388ee8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: remove weakly defined per-platform SiP handler

This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition

Tegra: remove weakly defined per-platform SiP handler

This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition.

Change-Id: Id4c7e69163d2635de1813f5a385ac874253a8da9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: remove weakly defined PSCI platform handlers

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-I

Tegra: remove weakly defined PSCI platform handlers

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: remove weakly defined platform setup handlers

This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some M

Tegra: remove weakly defined platform setup handlers

This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some MISRA defects.

The weakly defined handlers never get executed thus resulting in
lower coverage - function, function calls, statements, branches
and pairs.

Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Enable -Wredundant-decls warning check

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently,

Enable -Wredundant-decls warning check

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Tegra: bpmp: fix header file paths

This patch fixes the header file paths to include debug.h
from the right location.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If303792d2169158f

Tegra: bpmp: fix header file paths

This patch fixes the header file paths to include debug.h
from the right location.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If303792d2169158f436ae6aa5b6d7a4f88e28f7b

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