| c21a736d | 05-Jan-2022 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(mt8195): apply erratas of CA78 for MT8195
MT8195 uses Cortex A78 CPU, so we apply these erratas.
TEST=build pass
BUG=none
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5ce
feat(mt8195): apply erratas of CA78 for MT8195
MT8195 uses Cortex A78 CPU, so we apply these erratas.
TEST=build pass
BUG=none
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5ce3d5c490a12226bff4eb5a2d55687da0f74f0e
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| ab453050 | 09-Dec-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.com> |
feat(plat/mediatek/mt8195): improve SPM wakeup log
To enhance debug efficiency, modify wakeup log:
1. Redefine strings of wakeup reason for readability.
2. Indicate 26M clock on/off state of previou
feat(plat/mediatek/mt8195): improve SPM wakeup log
To enhance debug efficiency, modify wakeup log:
1. Redefine strings of wakeup reason for readability.
2. Indicate 26M clock on/off state of previous suspend.
3. Add warning log if SPM cannot get wakeup reason.
BUG=b:205201535
TEST=build pass
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Icb14ebb08958da225969abd3cdd9e471d232c7eb
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| 690cb126 | 15-Nov-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.
BUG=b:20
feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.
BUG=b:204347737
TEST=build pass
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I7c9f8490b8898008ba6844c34c9e80caa6066cbc
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| 20ef588e | 15-Nov-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
feat(plat/mediatek/mt8195): dump EMI MPU configurations
Add dump_emi_mpu_regions() to dump EMI MPU configurations.
BUG=b:204347737
TEST=build pass
Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1
feat(plat/mediatek/mt8195): dump EMI MPU configurations
Add dump_emi_mpu_regions() to dump EMI MPU configurations.
BUG=b:204347737
TEST=build pass
Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1b8f
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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| 296b5902 | 08-Nov-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Ke
feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Kernel space.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
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| 88906b44 | 01-Nov-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
Add APU SiP call support for start/stop mcu.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I3bec0b588a2884327ba645e95
feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
Add APU SiP call support for start/stop mcu.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I3bec0b588a2884327ba645e9568c0150436afa42
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| 339e4924 | 01-Nov-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8195 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
clock/pll register ranges.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If24cf21
feat(plat/mediatek/apu): add mt8195 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
clock/pll register ranges.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If24cf21318813babfc2c11f38891521c7106b58c
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| 964ee4e6 | 11-Nov-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(mt8195): use correct print format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit variables.
Change-Id: I09a8d
fix(mt8195): use correct print format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit variables.
Change-Id: I09a8d174694d4b170a6ef2e4a03df13adc829c00
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| c260b324 | 13-Oct-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): remove adsp event from wakeup source
Audio DSP is power-off when system suspend. Remove it from
wakeup source list to prevent unnecessary wakeup.
Signed-off-by: Edward-J
feat(plat/mdeiatek/mt8195): remove adsp event from wakeup source
Audio DSP is power-off when system suspend. Remove it from
wakeup source list to prevent unnecessary wakeup.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Id7251de9c8b9c9a4a4b2c41a310168d336035b9a
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| 3b994a75 | 10-Aug-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those
feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
BUG=b:192429713
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I02c6c862b6217bc84c83a09b533bd53ec19b06f7
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| 85e4d14d | 17-Sep-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
fix(plat/mediatek/mt8195): fix coverity fail
Add break to correct the driver flow.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie20f402d543fbf90172671e007fad30d5dc2ab10 |
| 75edd34a | 19-Aug-2021 |
Penny Jan <penny.jan@mediatek.com> |
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.
Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>
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| d562130e | 09-Jul-2021 |
Dawei Chien <dawei.chien@mediatek.com> |
feat(plat/mediatek/mt8195): add vcore-dvfs support
Add DVFSRC init flow.
Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> |
| 1f81ccce | 20-Jul-2021 |
Garmin Chang <garmin.chang@mediatek.com> |
fix(plat/mediatek/me8195): fix error setting for SPM
There is a error setting for SPM, so we need to fix this issue.
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a
fix(plat/mediatek/me8195): fix error setting for SPM
There is a error setting for SPM, so we need to fix this issue.
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a831fe48fd5bc3da9904db14c8a57
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| 49d3bd8c | 02-Jul-2021 |
Garmin Chang <garmin.chang@mediatek.com> |
feat(plat/mediatek/mt8195): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable M
feat(plat/mediatek/mt8195): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.
Change-Id: I3237199bc217bd3682f51d31284db5fd0324b396
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
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| 859e346b | 28-Jun-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8195): add SPM suspend driver
Support DRAM/MAINPLL/26M off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ib850
feat(plat/mediatek/mt8195): add SPM suspend driver
Support DRAM/MAINPLL/26M off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ib8502f9b0b4e47aa405e5449f0b6d483bd3f5d77
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| d336e093 | 28-Jun-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
Add drivers to support MCUSYS off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
Add drivers to support MCUSYS off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I388fd2318f471083158992464ecdf2181fc7d87a
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| 04818963 | 20-Jun-2021 |
Elly Chiang <elly.chiang@mediatek.com> |
feat(plat/mediatek/mt8195): add support for PTP3
Add PTP3 drivers to protect CPU excessive voltage drop
in CPU heavy loading.
Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d
Signed-off-by: Ell
feat(plat/mediatek/mt8195): add support for PTP3
Add PTP3 drivers to protect CPU excessive voltage drop
in CPU heavy loading.
Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d
Signed-off-by: Elly Chiang <elly.chiang@mediatek.com>
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| 9ff8b8ca | 18-Jun-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
fix(plat/mediatek/mt8195): extend MMU region size
In mt8195 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn
fix(plat/mediatek/mt8195): extend MMU region size
In mt8195 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.
This patch extends the MMU region 0 size to cover all mt8195 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.
Change-Id: I3a186ed71d0d963b59ae55e27a6d27a01fe4f638
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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| 7eb42237 | 12-Apr-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.c
feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iec73650e937bd20e25c18fa28d55ae29e68b10d3
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| c52a10a2 | 08-Apr-2021 |
Yidi Lin <yidi.lin@mediatek.com> |
mediatek: mt8195: add rtc power off sequence
mt8195 also uses mt6359p RTC. Revice mt8192 RTC and share the
driver with mt8195.
Change-Id: I20c73f6e0af67ef9d4c3d4e0ff373f93950e07db
Signed-off-by: Yi
mediatek: mt8195: add rtc power off sequence
mt8195 also uses mt6359p RTC. Revice mt8192 RTC and share the
driver with mt8195.
Change-Id: I20c73f6e0af67ef9d4c3d4e0ff373f93950e07db
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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| 0909819a | 08-Apr-2021 |
Yidi Lin <yidi.lin@mediatek.com> |
mediatek: mt8195: add power-off support
mt8195 also uses PMIC mt6359p. The only difference is the
pwrap register definition.
Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0
Signed-off-by: Yidi
mediatek: mt8195: add power-off support
mt8195 also uses PMIC mt6359p. The only difference is the
pwrap register definition.
Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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| fcc66173 | 07-Apr-2021 |
Yidi Lin <yidi.lin@mediatek.com> |
mediatek: mt8195: Add reboot function for PSCI
Add system_reset function in PSCI ops
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I177796e30198b0a53402093ee0917dda43074385 |
| aebd4dc8 | 31-Mar-2021 |
mtk20895 <zhiqiang.ma@mediatek.com> |
mediatek: mt8195: Add gpio driver
Add gpio driver.
Signed-off-by: mtk20895 <zhiqiang.ma@mediatek.com>
Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211 |
| 938fd425 | 29-Mar-2021 |
Yidi Lin <yidi.lin@mediatek.com> |
mediatek: mt8195: Add SiP service
Add the basic SiP service
Change-Id: I21fe9d85eac4be9101b12c4b6c28294c5b93cb5f
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> |