| dd47809e | 14-Aug-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
fix: marvell: Check the required libraries before building doimage
Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for e
fix: marvell: Check the required libraries before building doimage
Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for every
doimage build and suggest the required installation steps in case
of missing headers.
Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
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| fd1718a2 | 21-Mar-2018 |
Marcin Wojtas <mw@semihalf.com> |
plat: a8k: enable PMU overflow interrupt handler
This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on d
plat: a8k: enable PMU overflow interrupt handler
This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on demand in runtime.
Since it is possible to configure PMU interrupt trigger type
in the MADT ACPI table, it is enough to set it only once in EL3
during initialization.
Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| 155d01ff | 16-Nov-2017 |
Marcin Wojtas <mw@semihalf.com> |
marvell: pm: do not panic by default in cpu_standby
Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent o
marvell: pm: do not panic by default in cpu_standby
Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent on
the PM firmware running.
Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| b0f2361a | 17-Jul-2018 |
Marcin Wojtas <mw@semihalf.com> |
plat: marvell: a80x0: reconfigure CP0 PCIE0 windows
In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SAT
plat: marvell: a80x0: reconfigure CP0 PCIE0 windows
In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)
For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.
Change-Id: Ia8177194e542078772f90941eced81b231c16887
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| 5b0a152a | 17-Jul-2018 |
Marcin Wojtas <mw@semihalf.com> |
plat: marvell: a70x0: reconfigure CP0 PCIE2 windows
In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SAT
plat: marvell: a70x0: reconfigure CP0 PCIE2 windows
In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)
For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.
Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| de5cba28 | 13-Jun-2018 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
a8k: use the memory controller feature to protect the RT service region
Define the RT service space as secure with use of memory controller
trustzone feature. Thanks to this protection, any NS-Bootl
a8k: use the memory controller feature to protect the RT service region
Define the RT service space as secure with use of memory controller
trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS,
won't be able to access RT services (e.g. accidentally overwrite it,
which will at best result in RT services unavailability).
Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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