Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration

* changes:
plat/marvell: remove subversion from Marvell make files
drivers/marvell: check if TRNG unit is pr

Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration

* changes:
plat/marvell: remove subversion from Marvell make files
drivers/marvell: check if TRNG unit is present
plat/marvell: a8k: move efuse definitions to separate header
plat/marvell/armada: fix TRNG return SMC handling
drivers: marvell: comphy: add rx training on 10G port
plat/marvell/armada: postpone MSS CPU startup to BL31 stage
plat: marvell: armada: a8k: Fix LD selector mask
plat/marvell/armada: allow builds without MSS support
drivers: marvell: misc-dfx: extend dfx whitelist
drivers: marvell: add support for secure read/write of dfx register-set
ddr_phy: use smc calls to access ddr phy registers
drivers: marvell: thermal: use dedicated function for thermal SiPs
drivers: marvell: add thermal sensor driver and expose it via SIP service
fix: plat: marvell: fix MSS loader for A8K family

show more ...

plat/marvell/armada: postpone MSS CPU startup to BL31 stage

Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes s

plat/marvell/armada: postpone MSS CPU startup to BL31 stage

Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes should be
changed from defaults before the MSS CPU tries to access shared resources.
This patch starts to use CP MSS SRAM for FW load in both secure and
non-secure boot modes.
The FW loader inserts a magic number into MSS SRAM as an indicator of
successfully loaded FS during the BL2 stage and skips releasing the MSS
CPU from the reset state.
Then, at BL31 stage, the MSS CPU is released from reset following the
call to cp110_init function that handles all the required bus attributes
configurations.

Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

show more ...

fix: plat: marvell: fix MSS loader for A8K family

Wrong brakets caused MSS FW load timeout error:
ERROR: MSS DMA failed (timeout)
ERROR: MSS FW chunk 0 load failed
ERROR: SCP Image load failed

fix: plat: marvell: fix MSS loader for A8K family

Wrong brakets caused MSS FW load timeout error:
ERROR: MSS DMA failed (timeout)
ERROR: MSS FW chunk 0 load failed
ERROR: SCP Image load failed

This patch fixes the operator precedence in MSS FW load.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I78c215606bde112f40429926c51f5fa1e4334c13

show more ...

Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration

* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mappin

Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration

* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
include/drivers/marvell/mochi: add detection of secure mode
plat/marvell: fix SPD handling in dram port
marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
drivers/marvell/mochi: add support for cn913x in PCIe EP mode
drivers/marvell/mochi: add missing stream IDs configurations
plat/marvell/armada/a8k: support HW RNG by SMC
drivers/rambus: add TRNG-IP-76 driver

show more ...

plat/marvell/armada: cleanup MSS SRAM if used for copy

This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).

Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
S

plat/marvell/armada: cleanup MSS SRAM if used for copy

This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).

Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30099
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

show more ...

plat/marvell/armada/common/mss: use MSS SRAM in secure mode

The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image fro

plat/marvell/armada/common/mss: use MSS SRAM in secure mode

The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image from DRAM to IRAM.
This patch adds support for using the MSS SRAM as intermediate
storage. The MSS FW image is loaded by application CPU into the
MSS SRAM first, then transferred to MSS IRAM by MSS DMA.
Such change allows the CP MSS image load in secure mode.

Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>

show more ...

Merge changes I9feae1fc,I5cbe7192,I1867ece3,I85c2434a,If8edeeec, ... into integration

* changes:
plat: marvell: armada: mcbin: squash several IO windows into one
plat: marvell: armada: fix BL32

Merge changes I9feae1fc,I5cbe7192,I1867ece3,I85c2434a,If8edeeec, ... into integration

* changes:
plat: marvell: armada: mcbin: squash several IO windows into one
plat: marvell: armada: fix BL32 extra parameters usage
drivers: marvell: Fix the LLC SRAM driver
plat: marvell: armada: a8k: change CCU LLC SRAM mapping
plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS
drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW
plat: marvell: armada: move mg conf related code to appropriate driver
marvell: comphy: start AP FW when comphy AP mode selected
drivers: marvell: mg_conf_cm3: add basic driver
tools: doimage: change the binary image alignment to 16
tools: doimage: migrate to mbedtls v2.8 APIs

show more ...

plat: marvell: armada: move mg conf related code to appropriate driver

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Si

plat: marvell: armada: move mg conf related code to appropriate driver

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

show more ...

Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration

* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble:

Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration

* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble: ap807: clean-up PLL configuration sequence
ddr: a80x0: add DDR 32-bit mode support
plat: marvell: mci: perform mci link tuning for all mci interfaces
plat: marvell: mci: use more meaningful name for mci link tuning
plat: marvell: a8k: remove wrong or unnecessary comments
plat: marvell: ap807: enable snoop filter for ap807
plat: marvell: ap807: update configuration space of each CP
plat: marvell: ap807: use correct address for MCIx4 register
plat: marvell: add support for PLL 2.2GHz mode
plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic
marvell: armada: add extra level in marvell platform hierarchy

show more ...

marvell: armada: add extra level in marvell platform hierarchy

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
pla

marvell: armada: add extra level in marvell platform hierarchy

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

show more ...