Merge "fix(intel): f2sdram bridge quick write thru failed" into integration

Merge "feat(intel): add QSPI get devinfo mailbox cmd" into integration

fix(intel): add in watchdog for QSPI driver

ATF->Linux boot with QSPI boot source need to enable watchdog
so that it will not hang.

Change-Id: Id2a9ceebb1c89f711992a424f4394265efc6b388
Signed-off-b

fix(intel): add in watchdog for QSPI driver

ATF->Linux boot with QSPI boot source need to enable watchdog
so that it will not hang.

Change-Id: Id2a9ceebb1c89f711992a424f4394265efc6b388
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(intel): add QSPI get devinfo mailbox cmd

Linux RSU receive QSPI device info from SDM and report to user about
the device info.

Change-Id: Ib41692c9c4888c745a48a0609396aef0ca7fe25b
Signed-off-b

feat(intel): add QSPI get devinfo mailbox cmd

Linux RSU receive QSPI device info from SDM and report to user about
the device info.

Change-Id: Ib41692c9c4888c745a48a0609396aef0ca7fe25b
Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): f2sdram bridge quick write thru failed

This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.

Change-Id: Ib03498fbb

fix(intel): f2sdram bridge quick write thru failed

This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.

Change-Id: Ib03498fbb2d91e9fd85f6315091ff72cbe3f394d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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refactor: fix common misspelling of init*

Change-Id: I3fc95e8e53ef487fd5a559cda739aaea33d765a9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

fix(intel): update nand driver to match GHRD design

Update nand driver to match GHRD design, fix row
address calculation method and other misc updates.

Signed-off-by: Girisha Dengi <girisha.dengi@i

fix(intel): update nand driver to match GHRD design

Update nand driver to match GHRD design, fix row
address calculation method and other misc updates.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1cb3dda43e767ba243fbe89bfa18818db321c5c2

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Merge "feat(intel): enable SDMMC frontdoor load for ATF->Linux" into integration

feat(intel): enable query of fip offset on RSU

Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform

Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Sign

feat(intel): enable query of fip offset on RSU

Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform

Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>

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feat(intel): support query of fip offset using RSU

Query the fip binary from SPT table on RSU boot on Intel Agilex series.

Change-Id: I8856b49539f33272625d4c0a8c26b81b5864c4eb
Signed-off-by: Mahesh

feat(intel): support query of fip offset using RSU

Query the fip binary from SPT table on RSU boot on Intel Agilex series.

Change-Id: I8856b49539f33272625d4c0a8c26b81b5864c4eb
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>

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Merge "feat(intel): support wipe DDR after calibration" into integration

Merge "fix(intel): update from INFO to VERBOSE when print debug message" into integration

Merge changes Id85b2541,I4d253e2f into integration

* changes:
fix(intel): update system counter back to 400MHz
fix(intel): revert back to use L4 clock

Merge "fix(intel): update fcs crypto init code to check for mode" into integration

Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration

* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): suppor

Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration

* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): support QSPI ECC Linux for Stratix10
feat(intel): add in QSPI ECC for Linux

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fix(intel): update from INFO to VERBOSE when print debug message

Update from INFO to VERBOSE when print out debug message.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iefdbd44

fix(intel): update from INFO to VERBOSE when print debug message

Update from INFO to VERBOSE when print out debug message.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iefdbd44e711c0fd589bef454b42754cf9e3cd391

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feat(intel): support wipe DDR after calibration

After a calibration we cannot trust the DDR content. Let's explicitly
clear the DDR content using the built-in scrubber in this case.

Signed-off-by:

feat(intel): support wipe DDR after calibration

After a calibration we cannot trust the DDR content. Let's explicitly
clear the DDR content using the built-in scrubber in this case.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I6f429623f76a21f61f85efbb660cf65d99c04f56

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fix(intel): update system counter back to 400MHz

Due to design issue, updated system counter back to hardcoded 400MHz

Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Li

fix(intel): update system counter back to 400MHz

Due to design issue, updated system counter back to hardcoded 400MHz

Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): revert back to use L4 clock

Using mpu_peri as the clock source will caused the system
timer vary. System timer shall get from a static clock
source.

L4 and L3 clock are both the same at

fix(intel): revert back to use L4 clock

Using mpu_peri as the clock source will caused the system
timer vary. System timer shall get from a static clock
source.

L4 and L3 clock are both the same at the moment.
There shall be a hardware update to differentiate the clock pll.
To keep this as dormant function for now.

Change-Id: I4d253e2f24a74cbec59bfcbf0e8547abbe3643a8
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): support QSPI ECC Linux for Agilex

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loo

feat(intel): support QSPI ECC Linux for Agilex

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): support QSPI ECC Linux for N5X

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I65c7fd1bfc21baa6c45d9f8a0ee9618e6061e8d7
Signed-off-by: Jit Loon Lim <jit.loon.l

feat(intel): support QSPI ECC Linux for N5X

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I65c7fd1bfc21baa6c45d9f8a0ee9618e6061e8d7
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(intel): support QSPI ECC Linux for Stratix10

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I1cdacc0f10dfa2a969f0bc5086277fd9081d02e2
Signed-off-by: Jit Loon Lim <jit.

feat(intel): support QSPI ECC Linux for Stratix10

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I1cdacc0f10dfa2a969f0bc5086277fd9081d02e2
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(intel): add in QSPI ECC for Linux

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@in

feat(intel): add in QSPI ECC for Linux

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): add HPS remapper to remap base address for SDM

Remap base address for SDM to access DRAM.

Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e
Signed-off-by: Jit Loon Lim <jit.loon.lim@

fix(intel): add HPS remapper to remap base address for SDM

Remap base address for SDM to access DRAM.

Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration