Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration

* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): suppor

Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration

* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): support QSPI ECC Linux for Stratix10
feat(intel): add in QSPI ECC for Linux

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fix(intel): update from INFO to VERBOSE when print debug message

Update from INFO to VERBOSE when print out debug message.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iefdbd44

fix(intel): update from INFO to VERBOSE when print debug message

Update from INFO to VERBOSE when print out debug message.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iefdbd44e711c0fd589bef454b42754cf9e3cd391

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feat(intel): support wipe DDR after calibration

After a calibration we cannot trust the DDR content. Let's explicitly
clear the DDR content using the built-in scrubber in this case.

Signed-off-by:

feat(intel): support wipe DDR after calibration

After a calibration we cannot trust the DDR content. Let's explicitly
clear the DDR content using the built-in scrubber in this case.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I6f429623f76a21f61f85efbb660cf65d99c04f56

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feat(intel): support QSPI ECC Linux for Agilex

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loo

feat(intel): support QSPI ECC Linux for Agilex

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): add in QSPI ECC for Linux

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@in

feat(intel): add in QSPI ECC for Linux

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): add HPS remapper to remap base address for SDM

Remap base address for SDM to access DRAM.

Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e
Signed-off-by: Jit Loon Lim <jit.loon.lim@

fix(intel): add HPS remapper to remap base address for SDM

Remap base address for SDM to access DRAM.

Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration

Merge "fix(intel): update DDR range checking for Agilex5" into integration

Merge "fix(intel): update fcs functions to check ddr range" into integration

Merge "feat(intel): support SDM mailbox safe inject seu error for Linux" into integration

feat(intel): enable SDMMC frontdoor load for ATF->Linux

SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR f

feat(intel): enable SDMMC frontdoor load for ATF->Linux

SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR for Linux boot.

Change-Id: Ida303fb43ea63013a08083ce65952c5ad4e28f93
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): fix hardcoded mpu frequency ticks

This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06a

fix(intel): fix hardcoded mpu frequency ticks

This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): support SDM mailbox safe inject seu error for Linux

Linux RAS shall handle the SEU error received from SDM and report
an error message to user

Change-Id: I89181a388063ce9bd6f56b45b1851

feat(intel): support SDM mailbox safe inject seu error for Linux

Linux RAS shall handle the SEU error received from SDM and report
an error message to user

Change-Id: I89181a388063ce9bd6f56b45b1851ccb08582437
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): update DDR range checking for Agilex5

Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.

Change-Id: Iaecfa5daae48da0af46cc1831d

fix(intel): update DDR range checking for Agilex5

Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.

Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): update fcs functions to check ddr range

The src addr and dest addr of fcs functions are not checked against
their valid ddr range. Thus adding the ddr range checking to avoid
overlap/ove

fix(intel): update fcs functions to check ddr range

The src addr and dest addr of fcs functions are not checked against
their valid ddr range. Thus adding the ddr range checking to avoid
overlap/overwritten ddr address.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9b4d4155dd16d9d5d36e0c91e4a2600c17867daf

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fix(intel): update fcs crypto init code to check for mode

The shall code only limit ECB, CBC and CTR mode to flow through the init
function. Anything other than that, the code shall reject to preven

fix(intel): update fcs crypto init code to check for mode

The shall code only limit ECB, CBC and CTR mode to flow through the init
function. Anything other than that, the code shall reject to prevent
security vulnerability.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I702ce90e229188830f8936bee2999610e9559b8b

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Merge "fix(intel): update HPS bridges for Agilex5 SoC FPGA" into integration

Merge "fix(intel): read QSPI bank buffer data in bytes" into integration

Merge "feat(intel): restructure watchdog" into integration

Merge "fix(intel): update individual return result for hps and fpga bridges" into integration

Merge "fix(intel): update stream id to non-secure for SDM" into integration

fix(intel): read QSPI bank buffer data in bytes

Read QSPI bank buffer data in bytes to avoid
inter-bank read failures.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Change-Id: If768d7cdd36

fix(intel): read QSPI bank buffer data in bytes

Read QSPI bank buffer data in bytes to avoid
inter-bank read failures.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Change-Id: If768d7cdd362694df3f3c86c959afad01a523f21

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fix(intel): update individual return result for hps and fpga bridges

The code is designed to execute SOC2FPGA and LWSOC2FPGA first
then to F2SOC and both sharing the same result "return".
Thus when

fix(intel): update individual return result for hps and fpga bridges

The code is designed to execute SOC2FPGA and LWSOC2FPGA first
then to F2SOC and both sharing the same result "return".
Thus when F2SOC is executed, the "return" result will overwrite
SOC2FPGA "return" result even though it is not enabled.
Using 2 different "return" result to for each bridges and
return both of them at the end of the function to
avoid being overwritten.

Change-Id: Id9de3f416fe3020db35bc946135b175be2a7dc1e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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