intel: Fix argument type for mailbox driver

This patch comes as fixes for 'intel: Fix Coverity Scan Defects' patch.
Revert changing argument type from uint32_t to uint64_t to fix
incompatible cast i

intel: Fix argument type for mailbox driver

This patch comes as fixes for 'intel: Fix Coverity Scan Defects' patch.
Revert changing argument type from uint32_t to uint64_t to fix
incompatible cast issue. Fix said bug by using intermediate uint32_t
array as a more appropriate solution.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I344cdabd432cf0a0389b225c934b35d12f4c631d

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Merge "intel: Fix Coverity Scan Defects" into integration

intel: Fix Coverity Scan Defects

Fix mailbox driver incompatible cast bug and control flow issue that
was flagged by Coverity Scan.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.

intel: Fix Coverity Scan Defects

Fix mailbox driver incompatible cast bug and control flow issue that
was flagged by Coverity Scan.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065

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Merge changes from topic "sip-svc" into integration

* changes:
intel: Introduce SMC support for mailbox command
intel: Extend SiP service to support mailbox's RSU

intel: Extend SiP service to support mailbox's RSU

Introduce support for RSU that can be initiated through SMC calls.

Added features as below:
- RSU status
- RSU update
- RSU HPS notify
- RSU get s

intel: Extend SiP service to support mailbox's RSU

Introduce support for RSU that can be initiated through SMC calls.

Added features as below:
- RSU status
- RSU update
- RSU HPS notify
- RSU get sub-partition

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c

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Merge changes from topic "bridge-en" into integration

* changes:
intel: Add function to check fpga readiness
intel: Add bridge control for FPGA reconfig
intel: FPGA config_isdone() status quer

Merge changes from topic "bridge-en" into integration

* changes:
intel: Add function to check fpga readiness
intel: Add bridge control for FPGA reconfig
intel: FPGA config_isdone() status query
intel: System Manager refactoring
intel: Refactor reset manager driver
intel: Enable bridge access in Intel platform
intel: Modify non secure access function

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intel: Refactor reset manager driver

Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through

intel: Refactor reset manager driver

Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a

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Merge changes from topic "sip-svc" into integration

* changes:
intel: Implement platform specific system reset 2
intel: Enable SiP SMC secure register access

intel: Implement platform specific system reset 2

Add support for platform specific warm-reset through psci system reset 2.

- system_reset2 implementation that calls for l2 cache reset
- Check for

intel: Implement platform specific system reset 2

Add support for platform specific warm-reset through psci system reset 2.

- system_reset2 implementation that calls for l2 cache reset
- Check for magic number and request for warm reset in bl2
- Create a shared reset manager header file for Agilex and Stratix 10
- Clean up parameter info in plat_get_next_bl_params

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726

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Merge changes from topic "nonbl2-boot" into integration

* changes:
intel: stratix10: Modify BL31 parameter handling
intel: Modify BL31 address mapping
intel: stratix10: Enable uboot entrypoint

Merge changes from topic "nonbl2-boot" into integration

* changes:
intel: stratix10: Modify BL31 parameter handling
intel: Modify BL31 address mapping
intel: stratix10: Enable uboot entrypoint support

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intel: Modify BL31 address mapping

Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragm

intel: Modify BL31 address mapping

Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099

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Merge changes from topic "platform-refactor" into integration

* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform c

Merge changes from topic "platform-refactor" into integration

* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform code [2/5]
intel: Refactor common platform code [1/5]

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intel: Refactor common platform code [4/5]

Pull out SiP & PSCI service driver into socfpga common directory.
Remove deassert_peripheral_reset from cold reset procedure as it is not
needed.

Signed-o

intel: Refactor common platform code [4/5]

Pull out SiP & PSCI service driver into socfpga common directory.
Remove deassert_peripheral_reset from cold reset procedure as it is not
needed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd

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