intel: platform: Include GICv2 makefile

This patch update each Intel's platform makefiles to include GICv2
makefile instead of manually sourcing individual c files. This aligns
with latest changes f

intel: platform: Include GICv2 makefile

This patch update each Intel's platform makefiles to include GICv2
makefile instead of manually sourcing individual c files. This aligns
with latest changes from commit #1322dc94f7.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib1f446a6fc578f73a9ef86f9708ddf12d7d75f48

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plat: intel: Add FPGAINTF configuration to when configuring pinmux

FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Chan

plat: intel: Add FPGAINTF configuration to when configuring pinmux

FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019

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plat: intel: set DRVSEL and SMPLSEL for DWMMC

DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.

Signed-o

plat: intel: set DRVSEL and SMPLSEL for DWMMC

DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677

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plat: intel: Fix clock configuration bugs

This fixes a few issues on the Agilex clock configuration:
- Set clock manager into boot mode before configuring clock
- Fix wrong divisor used when calcula

plat: intel: Fix clock configuration bugs

This fixes a few issues on the Agilex clock configuration:
- Set clock manager into boot mode before configuring clock
- Fix wrong divisor used when calculating vcocalib
- PLL sync configuration should be read and then written
- Wait PLL lock after PLL sync configuration is done
- Clear interrupt bits instead of set interrupt bits after configuration

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70

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Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration

16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data stru

16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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intel: Enable EMAC PHY in Intel FPGA platform

This initializes the EMAC PHY in both Stratix 10 and Agilex,
without this, EMAC PHY wouldn't work correctly.

Change-Id: I7e6b9e88fd9ef472884fcf648e6001

intel: Enable EMAC PHY in Intel FPGA platform

This initializes the EMAC PHY in both Stratix 10 and Agilex,
without this, EMAC PHY wouldn't work correctly.

Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>

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Merge "intel: Change boot source selection" into integration

intel: Extend SiP service to support mailbox's RSU

Introduce support for RSU that can be initiated through SMC calls.

Added features as below:
- RSU status
- RSU update
- RSU HPS notify
- RSU get s

intel: Extend SiP service to support mailbox's RSU

Introduce support for RSU that can be initiated through SMC calls.

Added features as below:
- RSU status
- RSU update
- RSU HPS notify
- RSU get sub-partition

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c

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intel: Change boot source selection

Platform handoff structure no longer includes boot source selection.
Hence, those settings can now be configured through socfpga_plat_def.h.

Signed-off-by: Hadi

intel: Change boot source selection

Platform handoff structure no longer includes boot source selection.
Hence, those settings can now be configured through socfpga_plat_def.h.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6

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intel: agilex: Enable uboot BL31 loading

This patch enables uboot's spl entrypoint to BL31 and also handles
secondary cpus state during cold boot.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi

intel: agilex: Enable uboot BL31 loading

This patch enables uboot's spl entrypoint to BL31 and also handles
secondary cpus state during cold boot.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c

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intel: Add function to check fpga readiness

Create a function to check for fpga readiness, and move the checking out
of bridge enable function.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.ab

intel: Add function to check fpga readiness

Create a function to check for fpga readiness, and move the checking out
of bridge enable function.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0

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intel: Add bridge control for FPGA reconfig

This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.

Signed-o

intel: Add bridge control for FPGA reconfig

This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d

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intel: System Manager refactoring

Refactored system manager driver to be shared across both intel platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d0

intel: System Manager refactoring

Refactored system manager driver to be shared across both intel platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d

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intel: Refactor reset manager driver

Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through

intel: Refactor reset manager driver

Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a

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intel: Enable bridge access in Intel platform

Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.

Signed-off-by: Hadi

intel: Enable bridge access in Intel platform

Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f

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intel: Modify non secure access function

Combine both peripheral and bridge non-secure access code
into a single callable function

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@int

intel: Modify non secure access function

Combine both peripheral and bridge non-secure access code
into a single callable function

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70

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Merge "intel: Fix memory calibration" into integration

Remove redundant declarations.

In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by:

Remove redundant declarations.

In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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intel: Fix memory calibration

Increase calibration delay to cater for HPS 1st mode and
reduce clear emif delay which takes too long

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@in

intel: Fix memory calibration

Increase calibration delay to cater for HPS 1st mode and
reduce clear emif delay which takes too long

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4

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intel: Refactor common platform code [5/5]

Removes unused source code for BL2 and BL31 in platform.mk.
Clean-up unused header files, syntax fixes, and alphabetical
sorting post-refactoring

Signed-o

intel: Refactor common platform code [5/5]

Removes unused source code for BL2 and BL31 in platform.mk.
Clean-up unused header files, syntax fixes, and alphabetical
sorting post-refactoring

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd

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intel: Refactor common platform code [4/5]

Pull out SiP & PSCI service driver into socfpga common directory.
Remove deassert_peripheral_reset from cold reset procedure as it is not
needed.

Signed-o

intel: Refactor common platform code [4/5]

Pull out SiP & PSCI service driver into socfpga common directory.
Remove deassert_peripheral_reset from cold reset procedure as it is not
needed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd

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intel: Refactor common platform code [3/5]

Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.h

intel: Refactor common platform code [3/5]

Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716

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intel: Refactor common platform code [2/5]

Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.hali

intel: Refactor common platform code [2/5]

Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5

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intel: Refactor common platform code [1/5]

Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both

intel: Refactor common platform code [1/5]

Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d

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