Invalidate dcache build option for bl2 entry at EL3

Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cac

Invalidate dcache build option for bl2 entry at EL3

Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cache beforehand will crash the platform. Hence, this will provide an
option to skip the data cache invalidation upon bl2 entry at EL3

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06

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intel: agilex: Fix psci power domain off

Disable gic cpu interface for powered down cpu. This patch also removes
core reset during power off as core reset will be done during power on

Signed-off-by

intel: agilex: Fix psci power domain off

Disable gic cpu interface for powered down cpu. This patch also removes
core reset during power off as core reset will be done during power on

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673

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Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration

intel: agilex: HMC driver calculate DDR size

Driver will calculate DDR size instead of using hardcoded value

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I64

intel: agilex: HMC driver calculate DDR size

Driver will calculate DDR size instead of using hardcoded value

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde

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intel: agilex: Clear PLL lostlock bypass mode

To provide glitchless clock to downstream logic even if clock toggles

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-

intel: agilex: Clear PLL lostlock bypass mode

To provide glitchless clock to downstream logic even if clock toggles

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1

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Merge "intel: agilex: Fix memory controller driver" into integration

intel: agilex: Fix memory controller driver

Increase calibration delay, fix ddrio control config & nonsecure region
limit

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
C

intel: agilex: Fix memory controller driver

Increase calibration delay, fix ddrio control config & nonsecure region
limit

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b

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intel: agilex: Fix reliance on hard coded clock information

Extract clock information for UART, MMC & Watchdog from the clock manager

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@

intel: agilex: Fix reliance on hard coded clock information

Extract clock information for UART, MMC & Watchdog from the clock manager

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133

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Merge changes from topic "intel-plat-refactor" into integration

* changes:
intel: Platform common code refactor
intel: Platform common code refactor

intel: Platform common code refactor

Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359d

intel: Platform common code refactor

Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f

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intel: Platform common code refactor

Pull out common code from agilex and stratix10

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5

intel: Platform common code refactor

Pull out common code from agilex and stratix10

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc

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intel: agilex: Fix BL31 memory mapping

Previous config blocks ATF runtime service communications with SDM mailbox

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id

intel: agilex: Fix BL31 memory mapping

Previous config blocks ATF runtime service communications with SDM mailbox

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic97aa381d3ceb96395595ec192132859d626b8d1

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intel: agilex: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Enab

intel: agilex: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")

Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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intel: Adds support for Agilex platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef