fix(imx8mq): correct architected counter frequency

Different from other i.MX SoCs, which typically use a 24MHz reference clock,
the i.MX8MQ uses a 25MHz reference clock. As the architected timer clo

fix(imx8mq): correct architected counter frequency

Different from other i.MX SoCs, which typically use a 24MHz reference clock,
the i.MX8MQ uses a 25MHz reference clock. As the architected timer clock
frequency is directly sourced from the reference clock via a /3 divider this
SoC runs the timers at 8.33MHz.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: Ief36af9ffebce7cb75a200124134828d3963e744

show more ...

feat(imx8mq): enable optee fdt overlay support

Enable optee fdt overlay support

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I362

feat(imx8mq): enable optee fdt overlay support

Enable optee fdt overlay support

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I362445b93dc293a27c99b0d20a73f6b06ad0cd39

show more ...

feat(imx8mq): enable trusty for imx8mq

Add trusty support for imx8mq, default load address
and size for trusty os will be 0xfe000000 and 0x2000000.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off

feat(imx8mq): enable trusty for imx8mq

Add trusty support for imx8mq, default load address
and size for trusty os will be 0xfe000000 and 0x2000000.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2b35ee525b25b80bf6c9599a0adcc2d9f069aa41

show more ...

feat(imx8/imx8m): switch to xlat_tables_v2

spd trusty requires memory dynamic mapping feature to be
enabled, so we have to use xlat table library v2 instead
of v1.

Signed-off-by: Ji Luo <ji.luo@nxp

feat(imx8/imx8m): switch to xlat_tables_v2

spd trusty requires memory dynamic mapping feature to be
enabled, so we have to use xlat table library v2 instead
of v1.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2813af9c7878b1fc2a59e27619c5b643af6a1e91

show more ...

feat(imx8m): add imx csu/rdc enum type defines for imx8m

Add various enum type defines for CSU & RDC module for i.MX8M
family

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I70c050286919eab

feat(imx8m): add imx csu/rdc enum type defines for imx8m

Add various enum type defines for CSU & RDC module for i.MX8M
family

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I70c050286919eab51c6c553912bd4be57bc60f81

show more ...

feat(plat/imx8m): add system_reset2 implementation

Add imx_system_reset2 which extends existing SYSTEM_RESET. It provides
architectural reset definitions and vendor-specific resets.
By default warm

feat(plat/imx8m): add system_reset2 implementation

Add imx_system_reset2 which extends existing SYSTEM_RESET. It provides
architectural reset definitions and vendor-specific resets.
By default warm reset is triggered.

Also refactor existing implementation of wdog reset, add details about
each flag used.

Change-Id: Ia7348c32c385f1c61f8085776e81dd1e38ddda5c
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

show more ...

feat(plat/imx8m): add SiP call for secondary boot

In iMX8MM it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in case

feat(plat/imx8m): add SiP call for secondary boot

In iMX8MM it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in case the bootloader image is faulty OR can be
enforced by the user. To trigger that switch the
PERSIST_SECONDARY_BOOT bit should be set in GPR10 SRC register.
As the bit is retained after WARM reset, that permits to control
BootROM behavior regarding what boot image it will boot after
reset: primary or secondary.

This is useful for reliable bootloader A/B updates, as it permits
switching between two copies of bootloader at different offsets of
the same storage.

If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address
0x8400 for the primary image. If the PERSIST_SECONDARY_BOOT is 1,
the boot ROM reads that secondary image table from address 0x8200
on the boot media and uses the address specified in the table for
the secondary image.

Secondary Image Table contains the sector of secondary bootloader
image, exluding the offset to that image (explained below in the
note). To generate the Secondary Image Table, use e.g.:
$ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11'
'\x00\x00\x10\x0\x0\x00\x0\x0\x0'
> /tmp/sit.bin
$ hexdump -vC /tmp/sit.bin
00000000 00 00 00 00
00000004 00 00 00 00
00000008 33 22 11 00 <--- This is the "tag"
0000000c 00 10 00 00 <--- This is the "firstSectorNumber"
00000010 00 00 00 00

You can also use NXP script from [1][2] imx-mkimage tool for
SIT generation. Note that the firstSectorNumber is NOT the offset
of the IVT, but an offset of the IVT decremented by Image Vector
Table offset (Table 6-25. Image Vector Table Offset and Initial
Load Region Size for iMX8MM/MQ), so for secondary SPL copy at
offset 0x1042 sectors, firstSectorNumber must be 0x1000
(0x42 sectors * 512 = 0x8400 bytes offset).

In order to test redundant boot board should be closed and
SD/MMC manufacture mode disabled, as secondary boot is not
supported in the SD/MMC manufacture mode, which can be disabled
by blowing DISABLE_SDMMC_MFG (example for iMX8MM):
> fuse prog -y 2 1 0x00800000

For additional details check i.MX 8M Mini Apllication Processor
Reference Manual, 6.1.5.4.5 Redundant boot support for
expansion device chapter.

[1] https://source.codeaurora.org/external/imx/imx-mkimage/
[2] scripts/gen_sit.sh
Change-Id: I0a5cea7295a4197f6c89183d74b4011cada52d4c
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

show more ...

plat: imx8m: Fix the race condition during cpu hotplug

CPU hotplug & cpuidle have some race condition when doing CPU hotplug
stress test. different CPU cores have the chance to access the same
GPC r

plat: imx8m: Fix the race condition during cpu hotplug

CPU hotplug & cpuidle have some race condition when doing CPU hotplug
stress test. different CPU cores have the chance to access the same
GPC register(A53_AD), so lock is necessary to do exlusive access.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I1296592e05fa78429c3f0fac066951521db755e3

show more ...

plat: imx8m: Correct the imr mask reg offset

The number of gpc imr mask reg & the offset is different
on some SOC, so correct it & replace the magic number with
macro define.

Signed-off-by: Jacky B

plat: imx8m: Correct the imr mask reg offset

The number of gpc imr mask reg & the offset is different
on some SOC, so correct it & replace the magic number with
macro define.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74

show more ...

plat: imx8m: Move the gpc hw reg to a separate header file

Although the GPC provides the similar functions for all the
i.MX8M SoC family, the HW register offset and bit defines
still have some sligh

plat: imx8m: Move the gpc hw reg to a separate header file

Although the GPC provides the similar functions for all the
i.MX8M SoC family, the HW register offset and bit defines
still have some slight difference, so move the hw reg
offset & most of the bitfield defines in 'gpc_reg.h' that
is specific to each SoC.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I291c435fe98c2f6e6ff8fe0c715ff3a83daa6a0f

show more ...