Merge "feat(imx8mp): add BL31 PIE support" into integration

Merge changes from topic "imx8m-hab-support" into integration

* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and

Merge changes from topic "imx8m-hab-support" into integration

* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and map required memory blocks
feat(imx8mn): add hab and map required memory blocks
feat(imx8mm): add hab and map required memory blocks

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feat(imx8mp): add BL31 PIE support

Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). How important this is shows the back and forth
of the BL31_BASE addres

feat(imx8mp): add BL31 PIE support

Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). How important this is shows the back and forth
of the BL31_BASE address starting with TF-A v2.5. Since then the
BL31_BASE address wasn't stable and choosing the correct combination of
SPL version loadaddress and TF-A version loadaddr was tricky.

For the PIE support we only need to replace the BL31_BASE by the
BL31_START which is a relocatable symbol and to enable it by setting
ENABLE_PIE := 1.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I4214db1f27120f9f9cd1413ccd7a5a7d095ff45d

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feat(imx8m): add support for high assurance boot

Introduce support for High Assurance Boot (HABv4), which is used to
establish and extend the Root-of-Trust during FW loading at any given
boot stage.

feat(imx8m): add support for high assurance boot

Introduce support for High Assurance Boot (HABv4), which is used to
establish and extend the Root-of-Trust during FW loading at any given
boot stage.

This commit introduces support for HAB ROM Vector Table (RVT) API, which
is normally used by post-ROM code to authenticate additional boot images
(Kernel, FDT, FIT, etc.) that are taking part in the Root-of-Trust.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: I780d308369824fa4850844eb9e91768e417166a0

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Merge "fix: make TF-A use provided OpenSSL binary" into integration

fix: make TF-A use provided OpenSSL binary

Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linkin

fix: make TF-A use provided OpenSSL binary

Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linking issues as the system binary can end up being linked
against shared libraries provided in OPENSSL_DIR/lib if both binaries
(the system's and the on in OPENSSL_DIR/bin) are the same version.
This patch ensures that the binary used is always the one given by
OPENSSL_DIR to avoid those link issues.

Signed-off-by: Salome Thirot <salome.thirot@arm.com>
Change-Id: Ib534e06ebc8482e4391e376d3791a87968de4a99

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Merge changes Iec22dcab,Ib88b4b5d,I50cd6b82,If1167785,I9b3a08ef, ... into integration

* changes:
feat(imx8m): keep pu domains in default state during boot stage
feat(imx8m): add the PU power dom

Merge changes Iec22dcab,Ib88b4b5d,I50cd6b82,If1167785,I9b3a08ef, ... into integration

* changes:
feat(imx8m): keep pu domains in default state during boot stage
feat(imx8m): add the PU power domain support on imx8mm/mn
feat(imx8m): add the anamix pll override setting
feat(imx8m): add the ddr frequency change support for imx8m family
feat(imx8mn): enable dram retention suuport on imx8mn
feat(imx8mm): enable dram retention suuport on imx8mm
feat(imx8m): add dram retention flow for imx8m family

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feat(imx8m): add the ddr frequency change support for imx8m family

Add the DDR frequency change support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If1167785796b8678c351569b83d2922c66f6

feat(imx8m): add the ddr frequency change support for imx8m family

Add the DDR frequency change support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If1167785796b8678c351569b83d2922c66f6e530

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feat(imx8m): add dram retention flow for imx8m family

Add the dram retention flow for i.MX8M SoC family.

Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890
Signed-off-by: Jacky Bai <ping.bai@nxp.

feat(imx8m): add dram retention flow for imx8m family

Add the dram retention flow for i.MX8M SoC family.

Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

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Merge changes Idfd268cd,I362445b9,Ibea052d3,I28cb8f74,I501ae76a, ... into integration

* changes:
feat(imx8mp): enable BL32 fdt overlay support on imx8mp
feat(imx8mq): enable optee fdt overlay su

Merge changes Idfd268cd,I362445b9,Ibea052d3,I28cb8f74,I501ae76a, ... into integration

* changes:
feat(imx8mp): enable BL32 fdt overlay support on imx8mp
feat(imx8mq): enable optee fdt overlay support
feat(imx8mn): enable optee fdt overlay support
feat(imx8mm): enable optee fdt overlay support
feat(imx8mp): add trusty for imx8mp
feat(imx8mq): enable trusty for imx8mq
feat(imx8mn): enable Trusty OS for imx8mn
feat(imx8mm): enable Trusty OS on imx8mm
feat(imx8/imx8m): switch to xlat_tables_v2
feat(imx8m): enable the coram_s tz by default on imx8mn/mp
feat(imx8m): enable the csu init on imx8m
feat(imx8m): add a simple csu driver for imx8m family
refactor(imx8m): replace magic number with enum type
feat(imx8m): add imx csu/rdc enum type defines for imx8m
fix(imx8m): check the validation of domain id
feat(imx8m): enable conditional build for SDEI

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feat(imx8/imx8m): switch to xlat_tables_v2

spd trusty requires memory dynamic mapping feature to be
enabled, so we have to use xlat table library v2 instead
of v1.

Signed-off-by: Ji Luo <ji.luo@nxp

feat(imx8/imx8m): switch to xlat_tables_v2

spd trusty requires memory dynamic mapping feature to be
enabled, so we have to use xlat table library v2 instead
of v1.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2813af9c7878b1fc2a59e27619c5b643af6a1e91

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feat(imx8m): enable the csu init on imx8m

Enable the CSU init on i.MX8M SoC family. The 'csu_cfg' array
is just a placeholder for now as example with limited config listed.
In real use case,user can

feat(imx8m): enable the csu init on imx8m

Enable the CSU init on i.MX8M SoC family. The 'csu_cfg' array
is just a placeholder for now as example with limited config listed.
In real use case,user can add the CSU config as needed based on system design.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I1f7999efa346f18f6625ed8c478d088ed75f7833

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feat(imx8m): enable conditional build for SDEI

SDEI support on imx8m is an optional feature, so
make it conditional build, not enabled by default.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change

feat(imx8m): enable conditional build for SDEI

SDEI support on imx8m is an optional feature, so
make it conditional build, not enabled by default.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I6e7e8d77959ea352bc019f8468793992ec7ecfc4

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Merge changes from topic "imx8mp-tbbr" into integration

* changes:
feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP
refactor(plat/imx/imx8m): m

Merge changes from topic "imx8mp-tbbr" into integration

* changes:
feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP
refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common
feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout
refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common
feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

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feat(plat/imx/imx8m/imx8mp): enable Trusted Boot

This patch enables Trusted Boot on the i.MX8MP with BL2 doing image
verification from a FIP prior to hand-over to BL31.

Signed-off-by: Ying-Chun Liu

feat(plat/imx/imx8m/imx8mp): enable Trusted Boot

This patch enables Trusted Boot on the i.MX8MP with BL2 doing image
verification from a FIP prior to hand-over to BL31.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Iac1d1d62ea9858f67326a47c1e5ba377f23f9db5

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feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then

feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then BL2 will be built and BL31 will have its
address range modified upwards to accommodate. BL31 must be loaded from a
FIP in this case.

If NEED_BL2 is not specified then the current BL31 boot flow is unaffected
and u-boot SPL will load and execute BL31 directly.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I78914d6002755f733ea866127cb47982a00f9700

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Merge changes from topic "imx8m-sdei" into integration

* changes:
feat(plat/imx8m): add sdei support for i.MX8MP
feat(plat/imx8m): add sdei support for i.MX8MN

feat(plat/imx8m): add sdei support for i.MX8MP

Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled rout

feat(plat/imx8m): add sdei support for i.MX8MP

Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I8308c629448bd8adca9d3d25701adcf0c5a6afc2

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Merge changes from topic "imx8mp_basic_support" into integration

* changes:
plat: imx8mp: Add the basic support for i.MX8MP
plat: imx8m: Move the gpc hw reg to a separate header file

plat: imx8mp: Add the basic support for i.MX8MP

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Ma

plat: imx8mp: Add the basic support for i.MX8MP

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core Arm Cortex-A53 cluster and
Cortex-M7 low-power coprocessor, audio digital signal processor, machine
learning and graphics accelerators.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a

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