imx: imx_hab: Define a HAB header file

The High Assurance Boot or HAB is an on-chip method of providing a
root-of-trust from the reset vector to subsequent stages in the bootup
flow of the Cortex-A7

imx: imx_hab: Define a HAB header file

The High Assurance Boot or HAB is an on-chip method of providing a
root-of-trust from the reset vector to subsequent stages in the bootup
flow of the Cortex-A7 on the i.MX series of processors.

This patch adds a simple header file with pointer offsets of the provided
set of HAH API callbacks in the BootROM.

The relative offset of the function pointers is a constant and known
quantum, a software-contract between NXP and an implementation which is
defined in the NXP HAB documentation.

All we need is the correct base offset and then we can map the set of
function pointers relative to that offset.

imx_hab_arch.h provides the correct offset and the imx_hab.h hooks the
offset to the pre-determined callbacks.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>

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imx: imx_snvs: Add an SNVS core functionality

This patch adds snvs.c with a imx_snvs_init() function.

imx_snvs_init() sets up permissions of the RTC via the SNVS HPCOMR.

During previous work with

imx: imx_snvs: Add an SNVS core functionality

This patch adds snvs.c with a imx_snvs_init() function.

imx_snvs_init() sets up permissions of the RTC via the SNVS HPCOMR.

During previous work with OPTEE on the i.MX7 part we discovered that prior
to switching from secure-world to normal-world it is required to apply more
permissive permissions than are defaulted to in order for Linux to be able
to access the RTC and CAAM functionality in general.

This patch pertains to fixing the RTC permissions by way of the
HPCOMR.NPSWA_EN bit.

Once set non-privileged code aka Linux-kernel code has permissions to
access the SNVS where the RTC resides.

Perform that permissions fix in imx_snvs_init() now, with a later patch making
the call from our platform setup code.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_snvs: Define a SNVS header and memory map

This commit defines two things.

- The basic SNVS memory map. At the moment that is total overkill for the
permission bits we need to set inside

imx: imx_snvs: Define a SNVS header and memory map

This commit defines two things.

- The basic SNVS memory map. At the moment that is total overkill for the
permission bits we need to set inside the SNVS but, for the sake of
completeness define the whole SNVS area as a struct.

- The bits of the HPCOMR register

A permission fix will need to be applied to the SNVS block prior to
switching on TrustZone. All we need to do is waggle a bit in the HPCOMR
register. To do that waggle we first need to define the bits of the
HPCOMR register.

- A imx_snvs_init() function definition

Declare the snvs_init() function so that it can be called from our
platform setup code.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_csu: Add a simple CSU layer

- Add a header to define imx_csu_init().
- Defines the Central Security Unit's Config Security Level
permission bits.
- Define CSU_CSL_OPEN_ACCESS permission b

imx: imx_csu: Add a simple CSU layer

- Add a header to define imx_csu_init().
- Defines the Central Security Unit's Config Security Level
permission bits.
- Define CSU_CSL_OPEN_ACCESS permission bitmask
- Run a loop to setup peripheral CSU permissions

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_aips: Add initial AIPS support

This patch adds an initial AHB-to-IP TrustZone (AIPS-TZ) initialization
routine. Setting up the AIPSTZ controller is required to inform the SoC
interconnect f

imx: imx_aips: Add initial AIPS support

This patch adds an initial AHB-to-IP TrustZone (AIPS-TZ) initialization
routine. Setting up the AIPSTZ controller is required to inform the SoC
interconnect fabric which bus-masters can read/write and if the read/writes
are buffered.

For our purposes the initial configuration is for everything to be open. We
can lock-down later on as necessary.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_io_mux: Define an IO-mux layer

This patch defines:

- The full range of IO-mux register offsets relative to the base address of
the IO-mux block base address.

- The bits for muxing the U

imx: imx_io_mux: Define an IO-mux layer

This patch defines:

- The full range of IO-mux register offsets relative to the base address of
the IO-mux block base address.

- The bits for muxing the UART1 TX/RX lines.

- The bits for muxing the UART6 TX/RX lines.

- The pad control pad bits for the UART

Two functions are provided to configure pad muxes:

- void io_muxc_set_pad_alt_function(pad_mux_offset, alt_function)
Takes a pad_mux_offset and sets the alt_function bit-mask supplied.
This will have the effect of switching the pad into one of its defined
peripheral functions. These peripheral function modes are defined in the
NXP documentation and need to be referred to in order to correctly
configure a new alternative-function.

- void io_muxc_set_pad_features(pad_feature_offset, pad_features)
Takes a pad_feature_offset and applies a pad_features bit-mask to the
indicated pad.
This function allows the setting of PAD drive-strength, pull-up values,
hysteresis glitch filters and slew-rate settings.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx7: imx7_clock: usb: Initialize the USB core clocks

This patch initializes USB core clocks for the i.MX7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

imx7: imx7_clock: wdog: Initialize the watchdog clocks

This patch initializes the watchdog clocks for the i.MX7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

imx7: imx7_clock: uart: Add UART clock init logic

This patch adds an internal UART init routine that gets called from the
external facing clock init function.

In the first pass this call does an ex

imx7: imx7_clock: uart: Add UART clock init logic

This patch adds an internal UART init routine that gets called from the
external facing clock init function.

In the first pass this call does an explicit disable of all UART
clock-gates. Later changes will enable only the UART clock-gates we care
about.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_clock: usb: Add USB clock API

This set of patches adds a very minimal layer of USB enabling patches to
clock.c. Unlike the watchdog or UART blocks the USB clocks pertain to PHYs,
the main U

imx: imx_clock: usb: Add USB clock API

This set of patches adds a very minimal layer of USB enabling patches to
clock.c. Unlike the watchdog or UART blocks the USB clocks pertain to PHYs,
the main USB clock etc, not to different instances of the same IP block.

As a result this patch-set takes the clock CCGR clock identifier directly
rather than as an index of an instance of blocks of the same type.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_clock: wdog: Add watchdog clock API

This patch adds a set of functions to enable the clock for each of the
watchdog IP blocks.

Unlike the MMC and UART blocks, the watchdog blocks operate o

imx: imx_clock: wdog: Add watchdog clock API

This patch adds a set of functions to enable the clock for each of the
watchdog IP blocks.

Unlike the MMC and UART blocks, the watchdog blocks operate off of the one
root clock, only the clock-gates are enable/disabled individually.

As a consequence the function clock_set_wdog_clk_root_bits() is used to set
the root-slice just once for all of the watchdog blocks.

Future implementations may need to change this model but for now on the one
supported processor and similar NXP SoCs this model should work fine.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_clock: mmc: Add USDHC clock API

This patch adds an API to configure up the base USDHC clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct t

imx: imx_clock: mmc: Add USDHC clock API

This patch adds an API to configure up the base USDHC clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct th

imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
memory map.

- Defines the CCM Clock Gating Reg

imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
memory map.

- Defines the CCM Clock Gating Register which comes in a quadrumvirate
register set to read, set, clear and toggle individual clock gates into
one of four states based bitmask.

00: Domain clocks not needed
01: Domain clocks needed when in RUN
10: Domain clocks needed when in RUN and WAIT
11: Domain clocks needed all the time

- Defines clock control register bits

There are various quadrumvirate register blocks target-root, misc-root,
post-root, pre-root in the CCM.

The number of registers is huge but the four registers in each
quadrumvirate block contain the same bits, so the number of bit
definitions is actually quite low.

- Defines clock identifiers

An array of clock gates is provided in the CCM block. In order to index
that array and thus enable/disable clock gates for the right components,
we need to provide meaningful names to the indices.

Section 5.2.5 of the i.MX7 Solo Application Processor Reference Manual
Rev 0.1 provides the relevant details.

- Defines target mux select bits
This is a comprehensive definition of the target clock mux select bits.
These bits are required to correctly select the clock source. Defining
all of the bits up-front even for unused blocks in ATF means we can
switch on any block we want at a later date without having to write new
code in the clock-mux layer.

- Defines identifier indices into root-slice array
The root-slice array of control registers has a specific set of indices,
which differ from the clock-gate indices.

- Provides a clock gate enable/disable routine
Provides a clock-gate enable/disable routine via the set/clr
registers in a given clock-gate control register block.

This index passed should be one of the enums associated with CCM and
depending on enable/disable being passed either set or clr will be
written to.

The Domain0 bits are currently the only bits targeted by this write, more
work may need to be done on the domain bits in subsequent patches as a
result.

- imx: Adds set/clr routines to clock layer

Adds a set and clr routine to the clock layer. These routines allow us to
access the set and clear registers of the "target" block registers. These
are the registers where we select the clock source from the available list.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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libc: Fix all includes in codebase

The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb03

libc: Fix all includes in codebase

The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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imx: imx8qm: add domain off support

Add domain off support for Linux kernel's cpu
hot-plug feature, when there are cpu off request
from Linux kernel, TF-A will send command to
system controller to d

imx: imx8qm: add domain off support

Add domain off support for Linux kernel's cpu
hot-plug feature, when there are cpu off request
from Linux kernel, TF-A will send command to
system controller to do CPU power gate accordingly,
tested on i.MX8QM MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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imx: imx8qx: add domain suspend/resume support

Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered

imx: imx8qx: add domain suspend/resume support

Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered off and can be waked up if irq pending
in GIC, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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imx: imx8qx: add system reset support

Add system reset support for i.MX8QX,
when Linux kernel issues "reboot" command,
TF-A will send command to inform system
controller to reset whole board accordi

imx: imx8qx: add system reset support

Add system reset support for i.MX8QX,
when Linux kernel issues "reboot" command,
TF-A will send command to inform system
controller to reset whole board according
to board design, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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imx: imx8qx: add system off support

Add system power off support for i.MX8QX,
when Linux kernel issues "poweroff" command,
TF-A will send command to inform system
controller to power off whole board

imx: imx8qx: add system off support

Add system power off support for i.MX8QX,
when Linux kernel issues "poweroff" command,
TF-A will send command to inform system
controller to power off whole board according
to board design, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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Support for NXP's i.MX8QM SoC

NXP's i.MX8QM is an ARMv8 SoC with 2 clusters, 2 Cortex-A72
cores in one cluster and 4 Cortex-A53 in the other cluster,
and also has system controller (Cortex-M4) insid

Support for NXP's i.MX8QM SoC

NXP's i.MX8QM is an ARMv8 SoC with 2 clusters, 2 Cortex-A72
cores in one cluster and 4 Cortex-A53 in the other cluster,
and also has system controller (Cortex-M4) inside, documentation
can be found in below link:

https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES

This patch adds support for booting up SMP linux kernel (v4.9).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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Support for NXP's i.MX8QX SoC

NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and
system controller (Cortex-M4) inside, documentation can
be found in below link:

https://www.nxp.com/products/

Support for NXP's i.MX8QX SoC

NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and
system controller (Cortex-M4) inside, documentation can
be found in below link:

https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES

This patch adds support for booting up SMP linux kernel (v4.9).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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Support for NXP's imx SoC common function

This patch adds support for NXP's imx SoC common
function support like topology, gic implementation.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's imx SoC debug uart

Add NXP's imx SoC debug uart driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's i.MX8 SoCs IPC

NXP's i.MX8 SoCs have system controller (M4 core)
which takes control of clock management, power management,
partition management, PAD management etc., other
cluster

Support for NXP's i.MX8 SoCs IPC

NXP's i.MX8 SoCs have system controller (M4 core)
which takes control of clock management, power management,
partition management, PAD management etc., other
clusters like Cortex-A35 can send out command via MU
(Message Unit) to system controller for clock/power
management etc..

This patch adds basic IPC(inter-processor communication) support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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