refactor(tc): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I645f6e8638cedfa6ff92d07b93cbaf38bdb2e09f
Signed

refactor(tc): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I645f6e8638cedfa6ff92d07b93cbaf38bdb2e09f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(fvp): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signe

refactor(fvp): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "gr/cpu_rename" into integration

* changes:
chore: rename hayes to a520
chore: rename hunter to a720
chore: rename hunter_elp to cortex-x4

chore: rename hayes to a520

Rename Cortex-hayes to Cortes-A520

Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename hunter to a720

Rename cortex_hunter to cortex_a720

Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge "fix(fvp): adjust BL31 maximum size as per total SRAM size" into integration

chore: rename hunter_elp to cortex-x4

Rename hunter_elp to cortex-x4

Change-Id: I78c8c009d7bee14b4793dc1d950ed81273216831
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <M

fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "docs: remove deprecated tc0 from list of supported FVPs" into integration

Merge "feat(fvp): allow configurable FVP Trusted SRAM size" into integration

Merge changes from topic "RAS_REFACTORING" into integration

* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memor

Merge changes from topic "RAS_REFACTORING" into integration

* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memory region
feat(plat/arm): firmware first error handling support for base RAMs
feat(plat/arm): update common platform RAS implementation
feat(plat/sgi): remove RAS setup call from common code
refactor(plat/sgi): deprecate DMC-620 RAS support
fix(plat/common): register PLAT_SP_PRI only if not already registered
fix(plat/sgi): update PLAT_SP_PRI macro definition
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority

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docs: remove deprecated tc0 from list of supported FVPs

TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Si

docs: remove deprecated tc0 from list of supported FVPs

TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Id013fcecbe20700611463ef9eab8cb3ae09071cc

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feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform

To enable firmware first support for base element RAMs on RD-N2 platform
this patch adds following support
- Includes SDEI hea

feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform

To enable firmware first support for base element RAMs on RD-N2 platform
this patch adds following support
- Includes SDEI header to enable SDEI feature on RD-N2 platform.
- Add TZC configuration for CPER memory region for RD-N2 platform
variants. This region is marked for non-secure access as OSPM and
firmware need to access this region.
- Defines all base element RAM errors for RD-N2 platform variants.
- Defines a platform RAS event map and respective RAS config data
structure.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ideaed598f4924f3b9836d4d7e9ef76b9b7580b48

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feat(plat/arm): add memory map entry for CPER memory region

In firmware-first error handling approach the firmware consumes the
hardware fault interrupt, processes the error and notifies the fault t

feat(plat/arm): add memory map entry for CPER memory region

In firmware-first error handling approach the firmware consumes the
hardware fault interrupt, processes the error and notifies the fault to
OSPM. Firmware also shares the error information with the OSPM using a
standard format called Common Platform Error Record (CPER). The CPER is
placed in reserved memory that is shared between OSPM and the firmware.
On RD-N2 platform variants carve out a reserved memory space for the
CPER buffer. This patch enables CPER memory map region on RD-N2 platform
variants.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ib2645c90d4dc975f57bb143795f61f74f4f81494

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feat(plat/arm): firmware first error handling support for base RAMs

RD-N2 platform variants support base element RAM. The RAMs implement
ECC that detects ECC 1/2-bit errors and reports them via inte

feat(plat/arm): firmware first error handling support for base RAMs

RD-N2 platform variants support base element RAM. The RAMs implement
ECC that detects ECC 1/2-bit errors and reports them via interrupts. The
error information is reported as part of error record frames defined for
base element RAMs.

This patch provides reference error handler implementation to handle
1/2-bit RAS errors that occur on base element RAM's. On error event the
error handler reads the error records information and forwards the event
to secure partition. Secure partition creates a CPER record from this
error information. Finally the handler notifies the OS about the RAS
error using the SDEI notification mechanism.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ic209c714de6cd2d4c845198b03724940a2e1c240

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feat(plat/arm): update common platform RAS implementation

Refactor the RAS implementation to be used as common platform RAS
implementation for all the platforms. As part of refactoring this patch
ex

feat(plat/arm): update common platform RAS implementation

Refactor the RAS implementation to be used as common platform RAS
implementation for all the platforms. As part of refactoring this patch
extends support to configure interrupt as PPI interrupt type in addition
to currently supported SPI interrupts.

This patch defines a RAS config data structure to be defined by each
platform. The RAS config data structure carries the event map and size
information. Each platform code during initialization phase must define
this RAS config and register it with common platform RAS module.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4019b31386a7e9c197bcc83bdca47876ee854d0f

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feat(plat/sgi): remove RAS setup call from common code

In preparation of refactoring the support for platform error handling,
remove the call to RAS platform setup call from SGI specific common
code

feat(plat/sgi): remove RAS setup call from common code

In preparation of refactoring the support for platform error handling,
remove the call to RAS platform setup call from SGI specific common
code. This function will be called from platform code after the
refactoring.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: If4a87e0adf166b1c99bf5999f2f89efa6c7c6afc

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refactor(plat/sgi): deprecate DMC-620 RAS support

Remove DMC-620 specific code from platform RAS implementation. DMC-620
RAS support is not supported on SGI and RD platforms. The rest of the
platfor

refactor(plat/sgi): deprecate DMC-620 RAS support

Remove DMC-620 specific code from platform RAS implementation. DMC-620
RAS support is not supported on SGI and RD platforms. The rest of the
platform specific code maintained will be reused for supporting RAS
error handling on RD-N2 and later platforms.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ic03ae0e3298628330c5f7c25bafb0131f7b9d5b6

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fix(plat/sgi): update PLAT_SP_PRI macro definition

PLAT_SP_PRI EHF priority is defined to be same as the PLAT_RAS_PRI EHF
priority. But PLAT_RAS_PRIORITY is defined only if RAS_FFH_SUPPORT is
enable

fix(plat/sgi): update PLAT_SP_PRI macro definition

PLAT_SP_PRI EHF priority is defined to be same as the PLAT_RAS_PRI EHF
priority. But PLAT_RAS_PRIORITY is defined only if RAS_FFH_SUPPORT is
enabled. This patch defines priority value for PLAT_SP_PRI if
RAS_FFH_SUPPORT is not enabled.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ib3747317d2ecc088fbbf1f5f283726a330454c93

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fix(morello): configure platform specific secure SPIs

Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupt

fix(morello): configure platform specific secure SPIs

Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupts according to the Morello TRM and InfraSYSDESIGN4.0
specification.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I783a472d92601d86f1844f0d035dd0d036b2bfca

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Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve dir

Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve direct messaging validation

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fix(el3-spm): fix LSP direct message response

Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id

fix(el3-spm): fix LSP direct message response

Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I482c08d4657617adb00b0f3cf3c8ddc84f1bf7c8

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feat(fvp): allow configurable FVP Trusted SRAM size

In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you t

feat(fvp): allow configurable FVP Trusted SRAM size

In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you to configure a larger Trusted SRAM of 512KB.

This change introduces the `FVP_TRUSTED_SRAM_SIZE` build option, which
allows you to explicitly specify how much of the Trusted SRAM to
utilise, e.g.:

FVP_TRUSTED_SRAM_SIZE=384

This allows previously-failing configurations to build successfully by
utilising more than the originally-allocated 256KB of the Trusted SRAM
while maintaining compatibility with older configurations/models that
only require/have 256KB.

Change-Id: I8344d3718564cd2bd53f1e6860e2fe341ae240b0
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(build): include Cortex-A78AE cpu file for FVP" into integration

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
fix(gic600): fix gic600 maximum SPI ID

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