feat(neoverse-rd): add firmware definitions for third gen platforms

Add firmware definitions for the third generation of platforms. The
following files are added -

- nrd_css_fw_def3.h: for CSS firm

feat(neoverse-rd): add firmware definitions for third gen platforms

Add firmware definitions for the third generation of platforms. The
following files are added -

- nrd_css_fw_def3.h: for CSS firmware definitions
- nrd_ros_fw_def3.h : for RoS firmware definitions
- nrd_plat_arm_def3.h: for platform port macros

All the common files for these platforms are housed under nrd3
directory.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I085d609cfe1686d28d1c467fb34d45af47e00eb6

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feat(neoverse-rd): add RoS definitions for third gen platforms

Add RoS definitions for third generation of platforms. Common
definitions for such platforms would be housed in the nrd3 directory
unde

feat(neoverse-rd): add RoS definitions for third gen platforms

Add RoS definitions for third generation of platforms. Common
definitions for such platforms would be housed in the nrd3 directory
under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2062c71676f27b4d17a3069b955565670f62a76c

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feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in th

feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in the
nrd3 directory under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Id271ebdf5dcc1d7b598606c313208ab85662795d

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refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file

Add an explicit entry for HW_CONFIG in the BL2 CoT file for the Juno
platform, as the HW_CONFIG node has been removed from the common

refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file

Add an explicit entry for HW_CONFIG in the BL2 CoT file for the Juno
platform, as the HW_CONFIG node has been removed from the common CoT
file.

Change-Id: I8a1a22dd1023895cfc5730101fad20a80390ce17
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(fvp): add CoT desc dtsi

Adding CoT descriptor dtsi file to streamline fvp_tb_fw_config DTB file.

Change-Id: I0bbaef764b100ed0e749ec5f0c78a366398b3519
Signed-off-by: Lauren Wehrmeister <lau

refactor(fvp): add CoT desc dtsi

Adding CoT descriptor dtsi file to streamline fvp_tb_fw_config DTB file.

Change-Id: I0bbaef764b100ed0e749ec5f0c78a366398b3519
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(arm): add COT_DESC_IN_DTB option for Dualroot

Add support for BL2 to get the Dualroot chain of trust description
through the Firmware Configuration Framework (FCONF). This makes it
possible to

feat(arm): add COT_DESC_IN_DTB option for Dualroot

Add support for BL2 to get the Dualroot chain of trust description
through the Firmware Configuration Framework (FCONF). This makes it
possible to export the part of the Dualroot chain of trust enforced by
BL2 in BL2's configuration file (TB_FW_CONFIG DTB file). BL2 will parse
it when setting up the platform.

The feature can be enabled through the COT_DESC_IN_DTB=1 option. The
default behavior (COT_DESC_IN_DTB=0) remains to hard-code the Dualroot
CoT into BL2 images.

Change-Id: I3497b1daf14be09b5ce3a74d39df7551819255c2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(fvp): add Dualroot CoT in DTB support

Adding support for Dualroot CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file in
DTB format.

feat(fvp): add Dualroot CoT in DTB support

Adding support for Dualroot CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file in
DTB format. With this, the CoT description may be updated without
rebuilding BL2 image.

This feature can be enabled by building BL2 with COT_DESC_IN_DTB=1 and
COT=dualroot. The default behavior remains to embed the CoT description
into BL2 image.

Change-Id: I343931b145aa8a53b0a5d4b8aefb273ffb5a9163
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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refactor(tc): append binding for SMMU-700

The usage for SMMU-700 is not consistent across TC platforms:

SMMU-700 on TC2:

| FVP | FPGA
--------+-------+------
Display | Used | Us

refactor(tc): append binding for SMMU-700

The usage for SMMU-700 is not consistent across TC platforms:

SMMU-700 on TC2:

| FVP | FPGA
--------+-------+------
Display | Used | Used
GPU | Used | Used

SMMU-700 on TC3:

| FVP | FPGA
--------+-------+------
Display | No | No
GPU | Used | No

This commit changes to use append mode for SMMU-700 to bind it on TC2
and TC3 separately. As a result, the TC_IOMMU_EN configuration is not
used, remove it.

Change-Id: Ic4152eb4c8ef97bf27b8a97c3c6cb86e32a2e8eb
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): configure MCN rdalloc and wralloc mode

SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interfac

feat(tc): configure MCN rdalloc and wralloc mode

SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interface).

Change-Id: Ic8cd3ee988dd0772cfb9b639dea0cc335ab70539
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add dts entries for MCN PMU nodes

TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf dr

feat(tc): add dts entries for MCN PMU nodes

TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf driver can be used with perf.

Change-Id: I7e0ac5025231c3f19d5291292d4cae186accc544
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): enable MCN non-secure access to pmu counters on TC3

MCN PMU counters are by default non-accesible from non-secure world, so
enable the non-secure access to those PMU counters so that linux

feat(tc): enable MCN non-secure access to pmu counters on TC3

MCN PMU counters are by default non-accesible from non-secure world, so
enable the non-secure access to those PMU counters so that linux perf
driver can read them. FVP has a different address space size.

Change-Id: I2a3758faca5f7cab6d3146a1beb7b289eec0294d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "feat(tc): support full-HD resolution for the FVP model" into integration

Merge changes from topic "us_mhuv3" into integration

* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3

Merge changes from topic "us_mhuv3" into integration

* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3 for TC3
feat(tc): add MHUv3 DT binding for TC3
feat(tc): add MHUv3 doorbell support on TC3
refactor(tc): change tc_scmi_plat_info to single structure

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chore: rename Blackhawk to Cortex-X925

Rename Blackhawk to Cortex-X925.

Change-Id: I51e40a7bc6b8871c53c40d1f341853b1fd7fdf71
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename Chaberton to Cortex-A725

Rename Chaberton to Cortex-A725.

Change-Id: I981b22d3b37f1aa6e25ff1f35aa156fff9c30076
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge changes I710d1780,Ia9a59bde into integration

* changes:
feat(gpt): configure memory size protected by bitlock
feat(gpt): add support for large GPT mappings

feat(tc): support full-HD resolution for the FVP model

Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.

Change-Id: I5e37ae79b5ceac08

feat(tc): support full-HD resolution for the FVP model

Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.

Change-Id: I5e37ae79b5ceac088a18d5acf00ff4a557bb56aa
Signed-off-by: Sergio Alves <sergio.dasilvalves@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add MHUv3 addresses between RSS and AP

TC3 is upgraded to MHUv3. This patch adds the address of the MHU
channel to be used by TF-A for communications with the RSS.

Change-Id: I1bf5d72dc92

feat(tc): add MHUv3 addresses between RSS and AP

TC3 is upgraded to MHUv3. This patch adds the address of the MHU
channel to be used by TF-A for communications with the RSS.

Change-Id: I1bf5d72dc92bcd9d0509ba806095b24293875e85
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): specify MHU version based on platform

Platforms older than TC2 contain MHUv2 well as newer platforms contain
MHUv3. Set the Makefile variable accordingly.

Change-Id: I00b83a34908cdbf7d1d9

feat(tc): specify MHU version based on platform

Platforms older than TC2 contain MHUv2 well as newer platforms contain
MHUv3. Set the Makefile variable accordingly.

Change-Id: I00b83a34908cdbf7d1d9ac39728e3fa6ef449d2c
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add MHUv3 doorbell support on TC3

Enables the doorbell channels in MHUv3 for TC3.

Change-Id: Ib4f47df3e54f9182939ea6c1d8bc1a66a3c03094
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.

feat(tc): add MHUv3 doorbell support on TC3

Enables the doorbell channels in MHUv3 for TC3.

Change-Id: Ib4f47df3e54f9182939ea6c1d8bc1a66a3c03094
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(tc): change tc_scmi_plat_info to single structure

Currently, as the Total Compute system uses a single channel for MHU,
it's useless to define the structure 'tc_scmi_plat_info' as an array.

refactor(tc): change tc_scmi_plat_info to single structure

Currently, as the Total Compute system uses a single channel for MHU,
it's useless to define the structure 'tc_scmi_plat_info' as an array.
Change it as a single structure.

Change-Id: Iaa7c853327e7f5e67ccc14d12c5f0ef68d75dfd7
Signed-off-by: Leo Yan <leo.yan@arm.com>

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fix(juno): remove incorrect assert in sp min boot

There may be some valid configurations where a bootloader runs
before sp_min. In this case the bootloader may pass arguments through
the general pur

fix(juno): remove incorrect assert in sp min boot

There may be some valid configurations where a bootloader runs
before sp_min. In this case the bootloader may pass arguments through
the general purpose registers when passing control to sp_min causing
the assert to fail. Although sp_min may not use the content of the
registers requiring them to be zero seems unnecessary.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: I96fdc79626968830985bdd540f89e73b213de7d8

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feat(gpt): add support for large GPT mappings

This patch adds support for large GPT mappings using
Contiguous descriptors. The maximum size of supported
contiguous block in MB is defined in RME_GPT_

feat(gpt): add support for large GPT mappings

This patch adds support for large GPT mappings using
Contiguous descriptors. The maximum size of supported
contiguous block in MB is defined in RME_GPT_MAX_BLOCK
build parameter and takes values 0, 2, 32 and 512 and
by default set to 2 in make_helpers/defaults.mk.
Setting RME_GPT_MAX_BLOCK value to 0 disables use of
Contiguous descriptors.
Function gpt_tlbi_by_pa_ll() and its declaration
are removed from lib/aarch64/misc_helpers.S and
include/arch/aarch64/arch_helpers.h, because the
GPT library now uses tlbirpalos_xxx() functions.

Change-Id: Ia9a59bde1741c5666b4ca1de9324e6dfd6f734eb
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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fix(fvp): added ranges for linux

This extends the SPM's NS ranges for linux to do
the RXTX map.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I99b4f2c0355edb88be2484b445b97701e166cbfd

Merge changes from topic "ar/pmuSaveRestore" into integration

* changes:
feat(tc): add save/restore DSU PMU register support
feat(dsu): save/restore DSU PMU register
feat(plat): add platform A

Merge changes from topic "ar/pmuSaveRestore" into integration

* changes:
feat(tc): add save/restore DSU PMU register support
feat(dsu): save/restore DSU PMU register
feat(plat): add platform API that gets cluster ID

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