| 9ccc5a57 | 04-Apr-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> |
| bde2836f | 14-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove several warnings reported with W=2
Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.
The libraries are compiling with warnings (which turn in
Remove several warnings reported with W=2
Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed.
Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
show more ...
|
| 609e053c | 13-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which
Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed without heavy
structural changes.
Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
show more ...
|
| ae2e01b8 | 08-Mar-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
ROMLIB bug fixes
Fixed the below bugs:
1) Bug related to build flag V=1: if the flag was V=0, building with
ROMLIB would fail.
2) Due to a syntax bug in genwrappers.sh, index file entries marked as
ROMLIB bug fixes
Fixed the below bugs:
1) Bug related to build flag V=1: if the flag was V=0, building with
ROMLIB would fail.
2) Due to a syntax bug in genwrappers.sh, index file entries marked as
"patch" or "reserved" were ignored.
3) Added a prepending hash to constants that genwrappers is generating.
4) Due to broken dependencies, currently the inclusion functionality is
intentionally not utilised. This is why the contents of romlib/jmptbl.i
have been copied to platform specific jmptbl.i files. As a result of the
broken dependencies, when changing the index files, e.g. patching
functions, a clean build is always required. This is a known issue that
will be fixed in the future.
Change-Id: I9d92aa9724e86d8f90fcd3e9f66a27aa3cab7aaa
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
show more ...
|
| cc686492 | 18-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1892 from sandrine-bailleux-arm/sb/pauth
Pointer authentication fixes |
| 1fbb682a | 15-Mar-2019 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1888 from jts-arm/zeus
Introduce preliminary support for Neoverse Zeus |
| 01aa5247 | 13-Mar-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
fvp: Increase the size of the stack for FVP
When RECLAIM_INIT_CODE is 1, the stack is used to contain the .text.init
section. This is by default enable on FVP. Due to the size increase of
the .text.
fvp: Increase the size of the stack for FVP
When RECLAIM_INIT_CODE is 1, the stack is used to contain the .text.init
section. This is by default enable on FVP. Due to the size increase of
the .text.init section, the stack had to be adjusted contain it.
Change-Id: Ia392341970fb86c0426cf2229b1a7295453e2e32
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
show more ...
|
| 47102b35 | 13-Mar-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Put Pointer Authentication key value in BSS section
The dummy implementation of the plat_init_apiakey() platform API uses
an internal 128-bit buffer to store the initial key value used for
Pointer A
Put Pointer Authentication key value in BSS section
The dummy implementation of the plat_init_apiakey() platform API uses
an internal 128-bit buffer to store the initial key value used for
Pointer Authentication support.
The intent - as stated in the file comments - was for this buffer to
be write-protected by the MMU. Initialization of the buffer would be
performed before enabling the MMU, thus bypassing write protection
checks.
However, the key buffer ended up into its own read-write section by
mistake due to a typo on the section name ('rodata.apiakey' instead of
'.rodata.apiakey', note the leading dot). As a result, the linker
script was not pulling it into the .rodata output section.
One way to address this issue could have been to fix the section
name. However, this approach does not work well for BL1. Being the
first image in the boot flow, it typically is sitting in real ROM
so we don't have the capacity to update the key buffer at any time.
The dummy implementation of plat_init_apiakey() provided at the moment
is just there to demonstrate the Pointer Authentication feature in
action. Proper key management and key generation would have to be a
lot more careful on a production system.
Therefore, the approach chosen here to leave the key buffer in
writable memory but move it to the BSS section. This does mean that
the key buffer could be maliciously updated for intalling unintended
keys on the warm boot path but at the feature is only at an
experimental stage right now, this is deemed acceptable.
Change-Id: I121ccf35fe7bc86c73275a4586b32d4bc14698d6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
show more ...
|
| a4546e80 | 08-Oct-2018 |
John Tsichritzis <john.tsichritzis@arm.com> |
Introduce preliminary support for Neoverse Zeus
Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| cf6c30e0 | 07-Mar-2019 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
plat/arm: mhu: make mhu driver generic
MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic
plat/arm: mhu: make mhu driver generic
MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic MHU doorbell driver.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
show more ...
|
| c9aa2786 | 04-Mar-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1844 from chandnich/rename_sgiclark
css/sgi: replace all uses of Clark with new product names |
| d6bf24dc | 22-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
juno: Enable CPU errata workarounds
Change-Id: I7593f5ed89b9ef13b510e2259c909838c64ec56c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> |
| 27a257dc | 27-Feb-2019 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
css/sgi: replace all uses of Clark with new product names
Replace all uses of 'SGI_CLARK' with 'RD_N1E1_EDGE' and
'SGI_CLARK_HELIOS' with 'RD_E1_EDGE' as per the updated product
names
Change-Id: Ib
css/sgi: replace all uses of Clark with new product names
Replace all uses of 'SGI_CLARK' with 'RD_N1E1_EDGE' and
'SGI_CLARK_HELIOS' with 'RD_E1_EDGE' as per the updated product
names
Change-Id: Ib8136e421b1a46da1e5df58c6b1432d5c78d279b
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
show more ...
|
| 57bc6424 | 27-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1829 from antonio-nino-diaz-arm/an/pauth
Add Pointer Authentication (ARMv8.3-PAuth) support to the TF |
| ff6844c3 | 31-Jan-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
plat/arm: Implement ARMv8.3-PAuth interfaces
This feature is only supported on FVP.
Change-Id: I4e265610211d92a84bd2773c34acfbe02a1a1826
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 240f03b7 | 22-Feb-2019 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
board/rde1edge: rename sgiclarkh to rde1edge
Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with
'rde1edge' as per the updated product names.
Change-Id: I14e9b0332851798531de21d7
board/rde1edge: rename sgiclarkh to rde1edge
Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with
'rde1edge' as per the updated product names.
Change-Id: I14e9b0332851798531de21d70eb54f1e5557a7bd
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
show more ...
|
| f717eca9 | 22-Feb-2019 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
board/rdn1edge: rename sgiclarka to rdn1edge
Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with
'rdn1edge' as per the updated product names.
Change-Id: Idbc157c73477ec32f507ba2d
board/rdn1edge: rename sgiclarka to rdn1edge
Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with
'rdn1edge' as per the updated product names.
Change-Id: Idbc157c73477ec32f507ba2d4a4e907d8813374c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
show more ...
|
| 3f995f30 | 22-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1835 from jts-arm/rename
Apply official names to new Arm Neoverse cores |
| 8f73663b | 12-Dec-2018 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Support for Cortex A5 in FVP Versatile Express platform
Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex
plat/arm: Support for Cortex A5 in FVP Versatile Express platform
Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.
Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: Usama Arif <usama.arif@arm.com>
show more ...
|
| 6393c787 | 30-Nov-2018 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Introduce FVP Versatile Express platform.
This patch adds support for Versatile express FVP (Fast models).
Versatile express is a family of platforms that are based on ARM v7.
Currently th
plat/arm: Introduce FVP Versatile Express platform.
This patch adds support for Versatile express FVP (Fast models).
Versatile express is a family of platforms that are based on ARM v7.
Currently this port has only been tested on Cortex A7, although it
should work with other ARM V7 cores that support LPAE, generic timers,
VFP and hardware divide. Future patches will support other
cores like Cortex A5 that dont support features like LPAE
and hardware divide. This platform is tested on and only expected to
work on single core models.
Change-Id: I10893af65b8bb64da7b3bd851cab8231718e61dd
Signed-off-by: Usama Arif <usama.arif@arm.com>
show more ...
|
| 11088e39 | 19-Feb-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Rename Cortex-Helios to Neoverse E1
Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| da6d75a0 | 19-Feb-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Rename Cortex-Ares to Neoverse N1
Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| 0d28096c | 11-Feb-2019 |
Usama Arif <usama.arif@arm.com> |
Rename PLAT_ARM_BL31_RUN_UART* variable
The variable is renamed to PLAT_ARM_RUN_UART as
the UART is used outside BL31 as well.
Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a
Signed-off-by: Us
Rename PLAT_ARM_BL31_RUN_UART* variable
The variable is renamed to PLAT_ARM_RUN_UART as
the UART is used outside BL31 as well.
Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a
Signed-off-by: Usama Arif <usama.arif@arm.com>
show more ...
|
| 819dcd7c | 12-Feb-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
fvp: trusty: Move dynamic xlat enable to platform
Rather than letting the Trusty makefile set the option to enable dynamic
translation tables, make platforms do it themselves.
This also allows plat
fvp: trusty: Move dynamic xlat enable to platform
Rather than letting the Trusty makefile set the option to enable dynamic
translation tables, make platforms do it themselves.
This also allows platforms to replace the implementation of the
translation tables library as long as they use the same function
prototypes.
Change-Id: Ia60904f61709ac323addcb57f7a83391d9e21cd0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| a45ccf13 | 05-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1804 from antonio-nino-diaz-arm/an/cleanup
Minor cleanup |