arm_fpga: Add support for unknown MPIDs

This patch allows the system to fallback to a default CPU library
in case the MPID does not match with any of the supported ones.

This feature can be enabled

arm_fpga: Add support for unknown MPIDs

This patch allows the system to fallback to a default CPU library
in case the MPID does not match with any of the supported ones.

This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build
option to 1 (enabled by default only on arm_fpga platform).

This feature can be very dangerous on a production image and
therefore it MUST be disabled for Release images.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba

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Merge changes from topic "tc0_architecture_change" into integration

* changes:
plat: tc0: enable TZC
fdts: tc0: update MHUv2 interrupt number

Merge "plat/arm/css/sgi: Map flash used for mem_protect" into integration

Merge "plat/arm: Introduce and use libc_asm.mk makefile" into integration

plat/arm/css/sgi: Map flash used for mem_protect

The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which
indicates that the platform has mitigation for cold reboot attacks.

However, the fla

plat/arm/css/sgi: Map flash used for mem_protect

The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which
indicates that the platform has mitigation for cold reboot attacks.

However, the flash memory used for the mem_protect region was not
mapped. This results in a crash when an OS calls PSCI MEM_PROTECT.

To fix this map the flash region used for mem_protect.

Change-Id: Ia494f924ecfe2ce835c045689ba8f942bf0941f4
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>

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plat: tc0: enable TZC

Change-Id: Ic2bb8482f0b602f6b7850d4fa553448bc4931edc
Signed-off-by: Usama Arif <usama.arif@arm.com>

Merge "SPMC: adjust the number of EC context to max number of PEs" into integration

Merge changes from topic "ehf_common" into integration

* changes:
plat: tegra: Use generic ehf defines
ehf: use common priority level enumuration

SPMC: adjust the number of EC context to max number of PEs

According to [1] and in context of FF-A v1.0 a secure partition must
have either one EC (migratable UP) or a number of ECs equal to the
num

SPMC: adjust the number of EC context to max number of PEs

According to [1] and in context of FF-A v1.0 a secure partition must
have either one EC (migratable UP) or a number of ECs equal to the
number of PEs (pinned MP). Adjust the SPMC manifest such that the
number of ECs is equal to the number of PEs.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/components/
secure-partition-manager.html#platform-topology

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie8c7d96ae7107cb27f5b97882d8f476c18e026d4

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plat/arm: fvp: Increase BL2 maximum size

Increased BL2 maximum size when CoT descriptors are placed
in device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6466d2841e

plat/arm: fvp: Increase BL2 maximum size

Increased BL2 maximum size when CoT descriptors are placed
in device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6466d2841e189e7f15eb4f1a8db070542893cb5b

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lib: fconf: Implement a parser to populate CoT

Implemented a parser which populates the properties of
the CoT descriptors as per the binding document [1].
'COT_DESC_IN_DTB' build option is disabled

lib: fconf: Implement a parser to populate CoT

Implemented a parser which populates the properties of
the CoT descriptors as per the binding document [1].
'COT_DESC_IN_DTB' build option is disabled by default and can
be enabled in future for all Arm platforms by making necessary
changes in the memory map.
Currently, this parser is tested only for FVP platform.

[1]:
https://trustedfirmware-a.readthedocs.io/en/latest/components/cot-binding.html

Change-Id: I2f911206087a1a2942aa728de151d2ac269d27cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "tc0: increase SCP_BL2 size to 128 kB" into integration

Merge "SPM: Get rid of uint32_t array representation of UUID" into integration

tc0: increase SCP_BL2 size to 128 kB

The size of debug binaries of SCP has increased beyond the current
limit of 80kB set in platform. Hence, increase it to 128kB.

Change-Id: I5dbcf87f8fb35672b39ab

tc0: increase SCP_BL2 size to 128 kB

The size of debug binaries of SCP has increased beyond the current
limit of 80kB set in platform. Hence, increase it to 128kB.

Change-Id: I5dbcf87f8fb35672b39abdb942c0691fb339444a
Signed-off-by: Usama Arif <usama.arif@arm.com>

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plat/arm: rdn1edge: Correct mismatched parenthesis in makefile

This fixes build errors for rdn1edge

Change-Id: I63f7ebff68679e1e859f8786d4def4960c0f2ddf
Signed-off-by: Anders Dellien <anders.dellie

plat/arm: rdn1edge: Correct mismatched parenthesis in makefile

This fixes build errors for rdn1edge

Change-Id: I63f7ebff68679e1e859f8786d4def4960c0f2ddf
Signed-off-by: Anders Dellien <anders.dellien@arm.com>

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SPM: Get rid of uint32_t array representation of UUID

UUID's in the device tree files were stored in little endian. So
to keep all entries in these files RFC 4122 compliant, store them in
big endian

SPM: Get rid of uint32_t array representation of UUID

UUID's in the device tree files were stored in little endian. So
to keep all entries in these files RFC 4122 compliant, store them in
big endian then convert it to little endian when they are read so they
can be used in the UUID data structure.

Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Change-Id: I5674159b82b245104381df10a4e3291160d9b3b5

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Merge "plat/arm: Add dependencies to configuration files" into integration

plat/arm: Introduce and use libc_asm.mk makefile

Trace analysis of FVP_Base_AEMv8A 0.0/6063 model
running in Aarch32 mode with the build options
listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM

plat/arm: Introduce and use libc_asm.mk makefile

Trace analysis of FVP_Base_AEMv8A 0.0/6063 model
running in Aarch32 mode with the build options
listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.99% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch introduces new libc_asm.mk makefile which
replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 20.56%.
The number of CPU instructions (Inst) executed during
TF-A boot stage before start of BL33 in RELEASE builds
for different versions is presented in the tables below,
where:
- C TF-A: existing TF-A C code;
- C musl: "lightweight code" C "implementation of the
standard library for Linux-based systems"
https://git.musl-libc.org/cgit/musl/tree/src/string/memset.c
- Asm Opt: assemler version from "Arm Optimized Routines"
project
https://github.com/ARM-software/optimized-routines/blob/
master/string/arm/memset.S
- Asm Linux: assembler version from Linux kernel
https://github.com/torvalds/linux/blob/master/arch/arm/lib/memset.S
- Asm TF-A: assembler version from this patch

Aarch32:
+-----------+------+------+--------------+----------+
| Variant | Set | Size | Inst | Ratio |
+-----------+------+------+--------------+----------+
| C TF-A | T32 | 16 | 2122110003 | 1.000000 |
| C musl | T32 | 156 | 1643917668 | 0.774662 |
| Asm Opt | T32 | 84 | 1604810003 | 0.756233 |
| Asm Linux | A32 | 168 | 1566255018 | 0.738065 |
| Asm TF-A | A32 | 160 | 1525865101 | 0.719032 |
+-----------+------+------+--------------+----------+

AArch64:
+-----------+------+------------+----------+
| Variant | Size | Inst | Ratio |
+-----------+------+------------+----------+
| C TF-A | 28 | 2732497518 | 1.000000 |
| C musl | 212 | 1802999999 | 0.659836 |
| Asm TF-A | 140 | 1680260003 | 0.614917 |
+-----------+------+------------+----------+

This patch modifies 'plat\arm\common\arm_common.mk'
by overriding libc.mk makefile with libc_asm.mk and
does not effect other platforms.

Change-Id: Ie89dd0b74ba1079420733a0d76b7366ad0157c2e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge "arm_fpga: Add support to populate the CPU nodes in the DTB" into integration

arm_fpga: Add support to populate the CPU nodes in the DTB

At the moment BL31 dynamically discovers the CPU topology of an FPGA
system at runtime, but does not export it to the non-secure world.
Any

arm_fpga: Add support to populate the CPU nodes in the DTB

At the moment BL31 dynamically discovers the CPU topology of an FPGA
system at runtime, but does not export it to the non-secure world.
Any BL33 user would typically looks at the devicetree to learn about
existing CPUs.

This patch exports a minimum /cpus node in a devicetree to satisfy
the binding. This means that no cpumaps or caches are described.
This could be added later if needed.

An existing /cpus node in the DT will make the code bail out with a
message.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I589a2b3412411a3660134bdcef3a65e8200e1d7e

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plat/arm: Add dependencies to configuration files

This patch adds dependencies to the generated configuration
files that are included in the FIP. This fixes occasional
build errors that occur when t

plat/arm: Add dependencies to configuration files

This patch adds dependencies to the generated configuration
files that are included in the FIP. This fixes occasional
build errors that occur when the FIP happens to be built first.

Change-Id: I5a2bf724ba3aee13954403b141f2f19b4fd51d1b
Signed-off-by: Anders Dellien <anders.dellien@arm.com>

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Merge "plat/arm: Get the base address of nv-counters from device tree" into integration

sp_min: Avoid platform security reconfiguration

In the case of Juno AArch32, platform security configuration
gets done from both BL2 and SP_MIN(BL32) components when
JUNO_AARCH32_EL3_RUNTIME and RES

sp_min: Avoid platform security reconfiguration

In the case of Juno AArch32, platform security configuration
gets done from both BL2 and SP_MIN(BL32) components when
JUNO_AARCH32_EL3_RUNTIME and RESET_TO_SP_MIN build options
are set.
Fix is provided to avoid Platform security configuration from
SP_MIN when it is already done in BL2.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I702e91dacb4cdd2d10e339ddeaea91289bef3229

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plat/arm: Get the base address of nv-counters from device tree

Using the Fconf, register base address of the various nv-counters
(currently, trusted, non-trusted nv-counters) are moved to the
device

plat/arm: Get the base address of nv-counters from device tree

Using the Fconf, register base address of the various nv-counters
(currently, trusted, non-trusted nv-counters) are moved to the
device tree and retrieved during run-time. This feature is
enabled using the build option COT_DESC_IN_DTB.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I236f532e63cea63b179f60892cb406fc05cd5830

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ehf: use common priority level enumuration

'EHF' is used by RAS, SDEI, SPM_MM common frameworks.
If platform needs to plug-in specific handlers then
'PLAT_EHF_DESC' can be used to populate platform

ehf: use common priority level enumuration

'EHF' is used by RAS, SDEI, SPM_MM common frameworks.
If platform needs to plug-in specific handlers then
'PLAT_EHF_DESC' can be used to populate platform specific
priority levels.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: I37af7e0e48111f87b6982604bf5c15db3e05755d

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