| 5d5fb10f | 12-Feb-2021 |
Mikael Olsson <mikael.olsson@arm.com> |
plat/arm/juno: Add support to use hw_config in BL31
To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been
plat/arm/juno: Add support to use hw_config in BL31
To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been added that is included in the FIP and a Juno specific BL31
setup has been added to populate fconf with the hw_config.
Juno's BL2 setup has been updated to align it with the new behavior
implemented in the Arm FVP platform, where fw_config is passed in arg1
to BL31 instead of soc_fw_config. The BL31 setup is expected to use the
fw_config passed in arg1 to find the hw_config.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
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|
| 5eea0193 | 16-Apr-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Arm: Fix error message printing in board makefile
Remove an incorrect tabulation in front of an $(error) function call
outside of a recipe, which caused the following text to be displayed:
plat/a
Arm: Fix error message printing in board makefile
Remove an incorrect tabulation in front of an $(error) function call
outside of a recipe, which caused the following text to be displayed:
plat/arm/board/common/board_common.mk:36: *** recipe commences before first target. Stop.
instead of:
plat/arm/board/common/board_common.mk:36: *** "Unsupported ARM_ROTPK_LOCATION value". Stop.
Change-Id: I8592948e7de8ab0c4abbc56eb65a53eb1875a83c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 866e6721 | 15-Apr-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "scmi_v2_0" into integration
* changes:
drivers/arm/css/scmi: Update power domain protocol version to 2.0
tc0: update GICR base address |
| 69f2ace1 | 30-Mar-2021 |
Usama Arif <usama.arif@arm.com> |
tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642
tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
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|
| 3b9e06a6 | 13-Apr-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "plat/arm: don't provide NT_FW_CONFIG when booting hafnium" into integration |
| 2b6fc535 | 09-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
plat/arm: don't provide NT_FW_CONFIG when booting hafnium
NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
BL33, fvp platforms use this to pass measured boot configuration and
the
plat/arm: don't provide NT_FW_CONFIG when booting hafnium
NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
BL33, fvp platforms use this to pass measured boot configuration and
the x0 register is used to pass the base address of it.
In case of hafnium used as hypervisor in normal world, hypervisor
manifest is expected to be passed from BL31 and its base address is
passed in x0 register.
As only one of NT_FW_CONFIG or hypervisor manifest base address can be
passed in x0 register and also measured boot is not required for SPM so
disable passing NT_FW_CONFIG.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifad9d3658f55ba7d70f468a88997d5272339e53e
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|
| abe6ce1d | 25-Jan-2021 |
Heyi Guo <guoheyi@linux.alibaba.com> |
plat/arm/arm_image_load: refine plat_add_sp_images_load_info
Refine the function plat_add_sp_images_load_info() by saving the
previous node and only setting its next link when the current node is
va
plat/arm/arm_image_load: refine plat_add_sp_images_load_info
Refine the function plat_add_sp_images_load_info() by saving the
previous node and only setting its next link when the current node is
valid. This can reduce the check for the next node and simply the
total logic.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I4061428bf49ef0c3816ac22aaeb2e50315531f88
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|
| 47fe4c4f | 25-Jan-2021 |
Heyi Guo <guoheyi@linux.alibaba.com> |
plat/arm/arm_image_load: fix bug of overriding the last node
The traverse flow in function plat_add_sp_images_load_info() will find
the last node in the main load info list, with its
next_load_info=
plat/arm/arm_image_load: fix bug of overriding the last node
The traverse flow in function plat_add_sp_images_load_info() will find
the last node in the main load info list, with its
next_load_info==NULL. However this node is still useful and should not
be overridden with SP node info.
The bug will cause below error on RDN2 for spmd enabled:
ERROR: Invalid NT_FW_CONFIG DTB passed
Fix the bug by only setting the next_load_info of the last node in the
original main node list.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Icaee5da1f2d53b29fdd6085a8cc507446186fd57
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|
| 0a144dd4 | 16-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Add Cortex_A78C CPU lib
Add basic support for Cortex_A78C CPU.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56 |
| e5fa7459 | 29-Mar-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add Makalu ELP CPU lib" into integration |
| 59c2a027 | 25-Aug-2020 |
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> |
plat/sgi: tag dmc620 MM communicate messages with a guid
Define a GUID that should be used in the header of MM communicate
message originating due to a dmc620 ECC error interrupt. So the use
of SMC
plat/sgi: tag dmc620 MM communicate messages with a guid
Define a GUID that should be used in the header of MM communicate
message originating due to a dmc620 ECC error interrupt. So the use
of SMC ID in 'sgi_ras_ev_map' to represent the interrupt event is
removed.
In addition to this, update the dmc620 error record data structure to
use aux_data to indicate the dmc620 instance number on which the ECC
error interrupt occurred.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I18c8ef5ba6483bb1bce6464ee9be0c2aabec4baa
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|
| c0d55ef7 | 22-Jan-2021 |
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> |
plat/sgi: allow usage of secure partions on rdn2 platform
Add the secure partition mmap table and the secure partition boot
information to support secure partitions on RD-N2 platform. In addition
to
plat/sgi: allow usage of secure partions on rdn2 platform
Add the secure partition mmap table and the secure partition boot
information to support secure partitions on RD-N2 platform. In addition
to this, add the required memory region mapping for accessing the
SoC peripherals from the secure partition.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I2c75760d6c8c3da3ff4885599be420e924aeaf3c
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|
| f97b5795 | 17-Feb-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
board/rdv1mc: initialize tzc400 controllers
A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM m
board/rdv1mc: initialize tzc400 controllers
A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
across the Chips.
For use by secure software, configure the first chip's trustzone
controller to protect the upper 16MB of the memory of the first DRAM
block for secure accesses only. The other regions are configured for
non-secure read write access. For all the remote chips, all the DRAM
regions are allowed for non-secure read and write access.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1
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|
| 21803491 | 17-Feb-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/sgi: allow access to TZC controller on all chips
On a multi-chip platform, the boot CPU on the first chip programs the
TZC controllers on all the remote chips. Define a memory region map for
th
plat/sgi: allow access to TZC controller on all chips
On a multi-chip platform, the boot CPU on the first chip programs the
TZC controllers on all the remote chips. Define a memory region map for
the TZC controllers for all the remote chips and include it in the BL2
memory map table.
In addition to this, for SPM_MM enabled multi-chip platforms, increase
the number of mmap entries and xlat table counts for EL3 execution
context as well because the shared RAM regions and GIC address space of
remote chips are accessed.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I6f0b5fd22f9f28046451e382eef7f1f9258d88f7
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|
| 05b5c417 | 14-May-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/sgi: define memory regions for multi-chip platforms
For multi-chip platforms, add a macro to define the memory regions on
chip numbers >1 and its associated access permissions. These memory
reg
plat/sgi: define memory regions for multi-chip platforms
For multi-chip platforms, add a macro to define the memory regions on
chip numbers >1 and its associated access permissions. These memory
regions are marked with non-secure access.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: If3d6180fd8ea61f45147c39d3140d694abf06617
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|
| 5dae6bc7 | 15-Feb-2021 |
Thomas Abraham <thomas.abraham@arm.com> |
plat/sgi: allow access to nor2 flash and system registers from s-el0
Allow the access of system registers and nor2 flash memory region
from s-el0. This allows the secure parititions residing at s-el
plat/sgi: allow access to nor2 flash and system registers from s-el0
Allow the access of system registers and nor2 flash memory region
from s-el0. This allows the secure parititions residing at s-el0
to access these memory regions.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I3887a86770de806323fbde0d20fdc96eec6e0c3c
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|
| b4d548f1 | 16-Feb-2021 |
Thomas Abraham <thomas.abraham@arm.com> |
plat/sgi: define default list of memory regions for dmc620 tzc
Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
plat/sgi: define default list of memory regions for dmc620 tzc
Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
platforms. The default DMC-620 TZC memory regions are defined
considering the support for secure paritition as well.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db
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|
| d306eb80 | 16-Feb-2021 |
Thomas Abraham <thomas.abraham@arm.com> |
plat/sgi: improve macros defining cper buffer memory region
Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicabl
plat/sgi: improve macros defining cper buffer memory region
Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicable only
for platforms supported within plat/sgi. In addition to this, ensure
that these macros are defined only if the RAS_EXTENSION build option is
enabled.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I44df42cded18d9d3a4cb13e5c990e9ab3194daee
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|
| 513ba5c9 | 16-Feb-2021 |
Thomas Abraham <thomas.abraham@arm.com> |
plat/sgi: refactor DMC-620 error handling SMC function id
The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros
plat/sgi: refactor DMC-620 error handling SMC function id
The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros are
not applicable for all platforms supported under plat/sgi. So move these
macro definitions to sgi_ras.c file in which these are consumed. While
at it, remove the AArch32 and error injection function ids as these are
unused.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I249b54bf4c1b1694188a1e3b297345b942f16bc9
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|
| a8834474 | 16-Feb-2021 |
Thomas Abraham <thomas.abraham@arm.com> |
plat/sgi: refactor SDEI specific macros
The macros specific to SDEI defined in the sgi_base_platform_def.h are
not applicable for all the platforms supported by plat/sgi. So refactor
the SDEI specif
plat/sgi: refactor SDEI specific macros
The macros specific to SDEI defined in the sgi_base_platform_def.h are
not applicable for all the platforms supported by plat/sgi. So refactor
the SDEI specific macros into a new header file and include this file on
only on platforms it is applicable on.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I0cb7125334f02a21cae1837cdfd765c16ab50bf5
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|
| cb090c19 | 15-Mar-2021 |
johpow01 <john.powell@arm.com> |
Add Makalu ELP CPU lib
Add basic support for Makalu ELP processor core.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93 |
| ae030052 | 16-Mar-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "od/ffa_spmc_pwr" into integration
* changes:
SPM: declare third cactus instance as UP SP
SPMD: lock the g_spmd_pm structure
FF-A: implement FFA_SECONDARY_EP_REGISTER |
| 332649da | 15-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "matterhorn_elp" into integration
* changes:
plat: tc0: add matterhorn_elp_arm library to tc0
cpus: add Matterhorn ELP ARM cpu library |
| e96fc8e7 | 11-Feb-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many
SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
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|
| 5491208a | 12-Mar-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "linux_as_bl33" into integration
* changes:
plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31
plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33 |