| ddbf43b4 | 22-Apr-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp_r): update set_config_info function call
Pass NS-load address as ~0UL to the 'set_config_info' function while
updating FW_CONFIG device tree information since it is always loaded
into s
refactor(fvp_r): update set_config_info function call
Pass NS-load address as ~0UL to the 'set_config_info' function while
updating FW_CONFIG device tree information since it is always loaded
into secure memory.
Change-Id: I64e8531e0ad5cda63f14d838efb9da9cf20beea8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 046cb19b | 21-Apr-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(arm): update set_config_info function call
Pass NS-load address as ~0UL to the 'set_config_info' function while
updating FW_CONFIG device tree information since it is always loaded
into sec
refactor(arm): update set_config_info function call
Pass NS-load address as ~0UL to the 'set_config_info' function while
updating FW_CONFIG device tree information since it is always loaded
into secure memory.
Change-Id: Ia33adfa9e7b0392f62056053a2df7db321a74e22
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| fdbbd59e | 15-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "revert-14286-uart_segregation-VURJFOWMTM" into integration
* changes:
Revert "feat(sgi): deviate from arm css common uart related defi..."
Revert "feat(sgi): route TF-A
Merge changes from topic "revert-14286-uart_segregation-VURJFOWMTM" into integration
* changes:
Revert "feat(sgi): deviate from arm css common uart related defi..."
Revert "feat(sgi): route TF-A logs via secure uart"
Revert "feat(sgi): add page table translation entry for secure uart"
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| 64e04687 | 11-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Revert "feat(sgi): deviate from arm css common uart related defi..."
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstre
Revert "feat(sgi): deviate from arm css common uart related defi..."
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Change-Id: I28a370dd8b3a37087da621460eccc1acd7a30287
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| 162f7923 | 11-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Revert "feat(sgi): route TF-A logs via secure uart"
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted C
Revert "feat(sgi): route TF-A logs via secure uart"
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Change-Id: I7c488aed9fcb70c55686d705431b3fe017b8927d
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| 6127767a | 11-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Revert "feat(sgi): add page table translation entry for secure uart"
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstre
Revert "feat(sgi): add page table translation entry for secure uart"
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Change-Id: I9bec02496f826e184c6efa643f869b2eb3b52539
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| 7c6d460e | 10-Mar-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(fvp): op-tee sp manifest doesn't map gicd" into integration |
| 61fa5523 | 10-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(fvp): FCONF Trace Not Shown" into integration |
| 0c55c103 | 01-Feb-2022 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
fix(fvp): FCONF Trace Not Shown
Updating call order for arm_console_boot_init() and arm_bl31_early_platform_setup().
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: If932fff2
fix(fvp): FCONF Trace Not Shown
Updating call order for arm_console_boot_init() and arm_bl31_early_platform_setup().
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: If932fff2ee4282a0aacf8751fa81e7665b886467
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| 33d10ac8 | 13-Dec-2021 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(sgi): add page table translation entry for secure uart
Add page table translation entry for secure uart so that logs from
secure partition can be routed via the same.
Signed-off-by: Rohit Math
feat(sgi): add page table translation entry for secure uart
Add page table translation entry for secure uart so that logs from
secure partition can be routed via the same.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8574b31d5d138d9f94972deb903124f8c5b70ce4
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|
| 987e2b7c | 13-Dec-2021 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(sgi): route TF-A logs via secure uart
Route the boot, runtime and crash stage logs via secure UART port
instead of the existing use of non-secure UART. This aligns with the
security state the P
feat(sgi): route TF-A logs via secure uart
Route the boot, runtime and crash stage logs via secure UART port
instead of the existing use of non-secure UART. This aligns with the
security state the PE is in when logs are put out. In addition to this,
this allows consolidation of the UART related macros across all the
variants of the Neoverse reference design platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8896ae05eaedf06dead520659375af0329f31015
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| f2ccccaa | 13-Dec-2021 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(sgi): deviate from arm css common uart related definitions
The Neoverse reference design platforms will migrate to use different
set of secure and non-secure UART ports. This implies that the b
feat(sgi): deviate from arm css common uart related definitions
The Neoverse reference design platforms will migrate to use different
set of secure and non-secure UART ports. This implies that the board
specific macros defined in the common Arm platform code will no longer
be usable for Neoverse reference design platforms.
In preparation for migrating to a different set of UART ports, add a
Neoverse reference design platform specific copy of the board
definitions. The value of these definitions will be changed in
subsequent patches.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I39170848ecd81a7c1bbd3689bd905e45f9435f5c
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| 9ce15fe8 | 09-Feb-2022 |
Imre Kis <imre.kis@arm.com> |
fix(plat/arm): fix SP count limit without dual root CoT
Remove reserved range for platform provider owned SPs if the dual root
CoT is disabled and allow SPs to populate the range up to MAX_SP_IDS.
fix(plat/arm): fix SP count limit without dual root CoT
Remove reserved range for platform provider owned SPs if the dual root
CoT is disabled and allow SPs to populate the range up to MAX_SP_IDS.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ib4ec18f6530d2515ada21d2c0c388d55aa479d26
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| 69cde5cd | 25-May-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
fix(fvp): op-tee sp manifest doesn't map gicd
Following I2d274fa897171807e39b0ce9c8a28824ff424534:
Remove GICD registers S2 mapping from OP-TEE partition when it runs in a
secure partition on top of
fix(fvp): op-tee sp manifest doesn't map gicd
Following I2d274fa897171807e39b0ce9c8a28824ff424534:
Remove GICD registers S2 mapping from OP-TEE partition when it runs in a
secure partition on top of Hafnium.
The partition is not meant to access the GIC directly but use the
Hafnium provided interfaces.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1a38101f6ae9911662828734a3c9572642123f32
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|
| 92537e17 | 28-Feb-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(measured-boot): add RMM entry to event_log_metadata" into integration |
| 80b895ca | 23-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(board/rdedmunds): add support for rdedmunds variant" into integration |
| f4e3e1e8 | 10-Jan-2022 |
Tamas Ban <tamas.ban@arm.com> |
fix(measured-boot): add RMM entry to event_log_metadata
Platforms which support Realm world cannot boot up
properly if measured boot is enabled at build time.
An assertions occurs due to the missing
fix(measured-boot): add RMM entry to event_log_metadata
Platforms which support Realm world cannot boot up
properly if measured boot is enabled at build time.
An assertions occurs due to the missing RMM entry
in the event_log_metadata array.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I172f10a440797f7c9e1bc79dc72242b40c2521ea
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| 23ac80cc | 17-Feb-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(fvp): extend memory map to include all DRAM memory regions" into integration |
| e8035421 | 23-Dec-2021 |
Federico Recanati <federico.recanati@arm.com> |
fix(fvp): extend memory map to include all DRAM memory regions
Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
w
fix(fvp): extend memory map to include all DRAM memory regions
Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
whole address space.
Configuring all of them to allow tests to access memory also in those
higher memory regions.
FVP memory map:
https://developer.arm.com/documentation/100964/1116/Base-Platform/Base---memory/Base-Platform-memory-map
Note that last row is wrong, describing a non-existing 56bit address,
all region labels should be shifted upward.
Issue has been reported and next release will be correct.
Change-Id: I695fe8e24aff67d75e74635ba32a133342289eb4
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
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| ef515f0d | 19-Aug-2021 |
Tony K Nadackal <tony.nadackal@arm.com> |
feat(board/rdedmunds): add support for rdedmunds variant
Add initial support for RD-Edmunds platform. This platform is considered
as a variant of RD-N2 platform with only major change being the CPU
feat(board/rdedmunds): add support for rdedmunds variant
Add initial support for RD-Edmunds platform. This platform is considered
as a variant of RD-N2 platform with only major change being the CPU
which is Demeter instead of Neoverse-N2.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I939d9eac652fa9e76ad002ee5e6107aa79baa013
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| cf89fd57 | 27-Oct-2021 |
Satish Kumar <satish.kumar01@arm.com> |
feat(corstone1000): identify bank to load fip
Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the f
feat(corstone1000): identify bank to load fip
Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the flash. In this commit, bl2 reads the given flash
location to indentify the bank from which it should load fip from.
Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I7f0f4ffc97189c9deb99db44afcd966082ffbf21
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| 15594501 | 20-Sep-2021 |
Satish Kumar <satish.kumar01@arm.com> |
fix(corstone1000): change base address of FIP in the flash
More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of wher
fix(corstone1000): change base address of FIP in the flash
More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of where images are present.
Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: Ieaabe09374d707de18d36505c69b6c9a8c2ec2e9
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| a599c80d | 17-Nov-2021 |
Emekcan Aras <Emekcan.Aras@arm.com> |
feat(corstone1000): implement platform specific psci reset
This change implements platform specific psci reset
for the corstone1000.
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by
feat(corstone1000): implement platform specific psci reset
This change implements platform specific psci reset
for the corstone1000.
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I25f77234506416c3376ff4a028f6ea40ebe68437
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| 854d1c10 | 13-Oct-2021 |
Arpita S.K <Arpita.S.K@arm.com> |
feat(corstone1000): made changes to accommodate 3MB for optee
These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better reada
feat(corstone1000): made changes to accommodate 3MB for optee
These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better readability of the code
Moved uboot execution memory from CVM to DDR
Change-Id: I16657c6e336fe7c0fffdee1617d10af8a2c76732
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
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| 0260eb0d | 19-Jan-2022 |
Vishnu Banavath <vishnu.banavath@arm.com> |
build(corstone1000): rename diphda to corstone1000
diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.
Change-Id
build(corstone1000): rename diphda to corstone1000
diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.
Change-Id: I330f3a112d232b99b4721b6bf0236253b068dbba
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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