Merge "refactor(tc): neaten platform code after TC2 removal" into integration

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition table at
runtime, so a fixed offset is unnecessary. Also cleaned up the FIP
address handling comment for clarity.

Change-Id: I03f003a9307d66d16666eefcff1f45bb010779c9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes from topic "ja/ffa_v1_3" into integration

* changes:
feat(tc): bump SPMC version to FF-A v1.3 TC platform
feat(fvp): bump the SPMC version
feat(ff-a): bump SPMD FF-A version

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, an

build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, and platform integration logic to link with lib as a
static library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibEventLog is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I723f493033c178759a45ea04118e7cc295dc2438
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SP

Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry
feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
feat(spmd): get spmc manifest from xferlist

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feat(tc): bump SPMC version to FF-A v1.3 TC platform

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I196a0eb1bedb8bcc35b4524f04ea75f8c832a7f9

feat(fvp): bump the SPMC version

Bump the SPMC version in the fvp_spmc_optee_sp_manifest
to FF-A v1.3. The affected setup uses Hafnium as SPMC and
OPTEE as SP.

Signed-off-by: J-Alves <joao.alves@ar

feat(fvp): bump the SPMC version

Bump the SPMC version in the fvp_spmc_optee_sp_manifest
to FF-A v1.3. The affected setup uses Hafnium as SPMC and
OPTEE as SP.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I51d29832d8011dbdc9945f153805ba9b2b8663e7

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Merge "fix(spm): change the SMMUv3TestEngine being used" into integration

Merge changes from topic "bk/no_blx_setup" into integration

* changes:
fix: replace stray BL2_AT_EL3 with RESET_TO_BL2
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
re

Merge changes from topic "bk/no_blx_setup" into integration

* changes:
fix: replace stray BL2_AT_EL3 with RESET_TO_BL2
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
refactor: unify blx_setup() and blx_main()
fix(bl2): unify the BL2 EL3 and RME entrypoints

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feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR mac

feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR macros.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I0494738b9978ad72b3316a24d7811096c53f952b

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fix(spm): change the SMMUv3TestEngine being used

Use a test engine that's not connected via PCIe as those can't make
Secure accesses.

Change-Id: I6f7f235d022090189782381bc88e67de64c11927
Signed-off

fix(spm): change the SMMUv3TestEngine being used

Use a test engine that's not connected via PCIe as those can't make
Secure accesses.

Change-Id: I6f7f235d022090189782381bc88e67de64c11927
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[

refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[1] https://developer.arm.com/documentation/den0149/1-0alp0/

Change-Id: I15a652a021561edca16e79d127e6f08975cf1361
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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fix: replace stray BL2_AT_EL3 with RESET_TO_BL2

For FVP, patch 259b67c08 should have used the latter but introduced the
former. That was a mistake, correct it.

The nuvoton platform seems to have co

fix: replace stray BL2_AT_EL3 with RESET_TO_BL2

For FVP, patch 259b67c08 should have used the latter but introduced the
former. That was a mistake, correct it.

The nuvoton platform seems to have copied arm_def.h and would have been
missed at some point. Update that too.

Change-Id: I28123186bb4b69c5d5154dcdd24e5dee9d9e33b8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm

fvp_stmm_l2_sp_list.dts is used to load StandaloneMm with rust-spmc.

This sp information will be included into fvp_tb_fw_config.dts
by

feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm

fvp_stmm_l2_sp_list.dts is used to load StandaloneMm with rust-spmc.

This sp information will be included into fvp_tb_fw_config.dts
by specifying ARM_BL2_SP_LIST_DTS build option with this file.

Change-Id: I42b1ed9a04ac29b1a3c31f7267b337d4e3036c10
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry

For compatibility with SPMCs that obtain
event log information from DT_SPMC_MANIFEST,
ensure the event log is updated when TF-A

feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry

For compatibility with SPMCs that obtain
event log information from DT_SPMC_MANIFEST,
ensure the event log is updated when TF-A uses firmware handoff.

Change-Id: Iafc11c63c86c2ee67481e3085d2e8390d5f99cea
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition

PLAT_ARM_SPMC_SP_MANIFEST_SIZE is used to allocate transfer entry
when TF-A is built with TRANSFER_LIST to pass:
- StandaloneMm manifest w

feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition

PLAT_ARM_SPMC_SP_MANIFEST_SIZE is used to allocate transfer entry
when TF-A is built with TRANSFER_LIST to pass:
- StandaloneMm manifest with TL_TAG_DT_FFA_MANIFEST tag
in case of SPMC_AT_EL3

- SPMC manifest (i.e) rust-spmc.

Therefore, move the PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
under the TRNASFER_LIST & SPD_spmd condition and increase
the size of TRANSFER_LIST as much as PLAT_ARM_SPMC_SP_MANIFEST_SIZE

Change-Id: If5e4c184fcf3aa683554f6d49caf78a5f6bfc2d1
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(spmd): get spmc manifest from xferlist

When TRANSFER_LIST build option is used, arg0 doesn't pass the
SPMC manifest. but it should be passed to load SPMC.

For this, adds the spmc manifest entr

feat(spmd): get spmc manifest from xferlist

When TRANSFER_LIST build option is used, arg0 doesn't pass the
SPMC manifest. but it should be passed to load SPMC.

For this, adds the spmc manifest entry in the transfer list
with TL_TAG_DT_SPMC_MANIFEST tag and
let spmd load the spmc manifest from transfer list.

Change-Id: I3b84c3d8a17bba4ac94afe00e1e19044449360b0
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for

Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for BL2 separation

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feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONF

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONFIG_ADDR` with a common macro `ARM_HW_CONFIG_ADDR` for
accessing the device tree blob base address.

For FVP the DT address is set to use `ARM_PRELOADED_DTB_BASE` if
provided, falling back to a default address otherwise.

This provides a consistent mechanism for Arm platforms to define and
override the DTB base address used during kernel handoff. It reduces the
chance of misconfiguration, and simplifies platform integration.

Change-Id: Ib668dbb1de9d42cf41c0b0ee9a316f054891752a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Ch

feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Change-Id: I950883ea0c393a2a063ad9e51bb963cbac742705
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support" into integration

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single L1 table. The loop terminates when
the address of the first granule in range 'first'
exceeds address of the last granule (inclusive)
'last'.
This patch fixes the issue when fill_l1_cont_desc()
was iterating through all matching contiguous block
sizes 512, 32 and 2MB in a loop and filling consecutive
smaller descriptors instead of filling a single one with
a maximum size. This resulted for memory region 0x80000000
of size 1.5GB (3*512MB)to be filled with 2 512MB, 8 32MB and
128 2MB contiguous descriptors instead of 3 512MB descriptors
with build option RME_GPT_MAX_BLOCK=512.
This patch also removes unused definition of ARM_PAS_GPI_ANY
macro in fvp_pas_def.h.

Change-Id: I9fcff512af306a57d17dee0bade74d2f3f79b5e9
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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