| caf4eca1 | 20-Feb-2018 |
Soby Mathew <soby.mathew@arm.com> |
ARM Platforms: Add CASSERT for BL2_BASE
Change-Id: I93e491fde2a991fc39584c2762f33cbea40541e3
Signed-off-by: Soby Mathew <soby.mathew@arm.com> |
| 81bf6aae | 20-Feb-2018 |
Soby Mathew <soby.mathew@arm.com> |
ARM Platforms: Don't build BL1 and BL2 if RESET_TO_SP_MIN=1
Change-Id: Iadb21bb56f2e61d7e6aec9b3b3efd30059521def
Signed-off-by: Soby Mathew <soby.mathew@arm.com> |
| f2c83c1a | 25-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: Fix console address for flush
The console core flush API expects the base address in the first
register, but ARM helpers currently sets the second register with the
base address. This
ARM platforms: Fix console address for flush
The console core flush API expects the base address in the first
register, but ARM helpers currently sets the second register with the
base address. This causes an assert failure.
This patch fixes that.
Change-Id: Ic54c423cd60f2756902ab3cfc77b3de2ac45481e
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 33950dd8 | 26-Jan-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Build: change the first parameter of TOOL_ADD_IMG to lowercase
In the next commit, I need the image name in lowercase because
output files are generally named in lowercase.
Unfortunately, TOOL_ADD_
Build: change the first parameter of TOOL_ADD_IMG to lowercase
In the next commit, I need the image name in lowercase because
output files are generally named in lowercase.
Unfortunately, TOOL_ADD_IMG takes the first argument in uppercase
since we generally use uppercase Make variables.
make_helpers/build_macros.mk provides 'uppercase' macro to convert
a string into uppercase, but 'lowercase' does not exist. We can
implement it if we like, but it would be more straightforward to
change the argument of TOOL_ADD_IMG.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| c939d13a | 26-Jan-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Build: rename FIP_ADD_IMG to TOOL_ADD_IMG
Now FIP_ADD_IMG takes care of both fiptool and cert_create
symmetrically. Rename it so that it matches the behavior.
Signed-off-by: Masahiro Yamada <yamad
Build: rename FIP_ADD_IMG to TOOL_ADD_IMG
Now FIP_ADD_IMG takes care of both fiptool and cert_create
symmetrically. Rename it so that it matches the behavior.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 1dc0714f | 26-Jan-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Build: merge build macros between FIP_ and FWU_FIP_
The build system supports generating two FIP images, fip and fwu_fip.
Accordingly, we have similar build macros.
FIP_ADD_PAYLOAD <--> FWU_F
Build: merge build macros between FIP_ and FWU_FIP_
The build system supports generating two FIP images, fip and fwu_fip.
Accordingly, we have similar build macros.
FIP_ADD_PAYLOAD <--> FWU_FIP_ADD_PAYLOAD
CERT_ADD_CMD_OPT <--> FWU_CERT_ADD_CMD_OPT
FIP_ADD_IMG <--> FWU_FIP_ADD_IMG
The duplicated code increases the maintenance burden. Also, the build
rule of BL2U looks clumsy - we want to call MAKE_BL to compile it from
source files, but we want to put it in fwu_fip. We can not do it in a
single macro call since the current MAKE_BL does not support fwu_fip.
To refactor those in a clean way is to support one more argument to
specify the FIP prefix. If it is empty, the images are targeted to
fip, whereas if the argument is "FWU_", targeted to fwu_fip.
The build macros prefixed with FWU_ go away.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 81528dbc | 17-Nov-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
bl2-el3: Add BL2 at EL3 support in FVP
This patch add supports for the new API added for BL2 at EL3 for
FVP. We don't have a non-TF Boot ROM for FVP, but this option can be
tested setting specific p
bl2-el3: Add BL2 at EL3 support in FVP
This patch add supports for the new API added for BL2 at EL3 for
FVP. We don't have a non-TF Boot ROM for FVP, but this option can be
tested setting specific parameters in the model.
The bl2 image is loaded directly in memory instead of being loaded
by a non-TF Boot ROM and the reset address is changed:
--data cluster0.cpu0=bl2.bin@0x4001000
-C cluster0.cpu0.RVBAR=0x4001000
These parameters mean that in the cold boot path the processor will
jump to BL2 again. For this reason, BL2 is loaded in dram in this
case, to avoid other images reclaiming BL2 memory.
Change-Id: Ieb2ff8535a9e67ccebcd8c2212cad366e7776422
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
show more ...
|
| 66db10ca | 02-Jan-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Move TSP to TZC secured DRAM
To allow BL31 to grow in SRAM, move TSP in TZC secured DRAM
by default.
Increase the BL31 max limit by one page.
Change-Id: Idd3479be02f0f9bafac2f275376d7db0c2015431
S
Move TSP to TZC secured DRAM
To allow BL31 to grow in SRAM, move TSP in TZC secured DRAM
by default.
Increase the BL31 max limit by one page.
Change-Id: Idd3479be02f0f9bafac2f275376d7db0c2015431
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
show more ...
|
| 7bdf0c1f | 08-Dec-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: Allow platforms to define SDEI events
With this patch, ARM platforms are expected to define the macros
PLAT_ARM_SDEI_PRIVATE_EVENTS and PLAT_ARM_SDEI_SHARED_EVENTS as a list
of privat
ARM platforms: Allow platforms to define SDEI events
With this patch, ARM platforms are expected to define the macros
PLAT_ARM_SDEI_PRIVATE_EVENTS and PLAT_ARM_SDEI_SHARED_EVENTS as a list
of private and shared events, respectively. This allows for individual
platforms to define their own events.
Change-Id: I66851fdcbff83fd9568c2777ade9eb12df284b49
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| fb48b970 | 13-Nov-2017 |
Soby Mathew <soby.mathew@arm.com> |
ARM Platforms: Change the TZC access permissions for EL3 payload
This patch allows non-secure bus masters to access TZC region0 as well
as the EL3 Payload itself.
Change-Id: I7e44f2673a2992920d4150
ARM Platforms: Change the TZC access permissions for EL3 payload
This patch allows non-secure bus masters to access TZC region0 as well
as the EL3 Payload itself.
Change-Id: I7e44f2673a2992920d41503fb4c57bd7fb30747a
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
show more ...
|
| 281a08cc | 13-Oct-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Refactor Statistical Profiling Extensions implementation
Factor out SPE operations in a separate file. Use the publish
subscribe framework to drain the SPE buffers before entering secure
world. Ad
Refactor Statistical Profiling Extensions implementation
Factor out SPE operations in a separate file. Use the publish
subscribe framework to drain the SPE buffers before entering secure
world. Additionally, enable SPE before entering normal world.
A side effect of this change is that the profiling buffers are now
only drained when a transition from normal world to secure world
happens. Previously they were drained also on return from secure
world, which is unnecessary as SPE is not supported in S-EL1.
Change-Id: I17582c689b4b525770dbb6db098b3a0b5777b70a
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
show more ...
|
| 0baec2ab | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: Enable SDEI
Support SDEI on ARM platforms using frameworks implemented in earlier
patches by defining and exporting SDEI events: this patch defines the
standard event 0, and a handful
ARM platforms: Enable SDEI
Support SDEI on ARM platforms using frameworks implemented in earlier
patches by defining and exporting SDEI events: this patch defines the
standard event 0, and a handful of shared and private dynamic events.
Change-Id: I9d3d92a92cff646b8cc55eabda78e140deaa24e1
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 0bef0edf | 24-Oct-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: Define exception macros
Define number of priority bits, and allocate priority levels for SDEI.
Change-Id: Ib6bb6c5c09397f7caef950c4caed5a737b3d4112
Signed-off-by: Jeenu Viswambharan
ARM platforms: Define exception macros
Define number of priority bits, and allocate priority levels for SDEI.
Change-Id: Ib6bb6c5c09397f7caef950c4caed5a737b3d4112
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 781f4aac | 19-Oct-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: Provide SDEI entry point validation
Provide a strong definition for plat_sdei_validate_sdei_entrypoint()
which translates client address to Physical Address, and then validating
the a
ARM platforms: Provide SDEI entry point validation
Provide a strong definition for plat_sdei_validate_sdei_entrypoint()
which translates client address to Physical Address, and then validating
the address to be present in DRAM.
Change-Id: Ib93eb66b413d638aa5524d1b3de36aa16d38ea11
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 71e7a4e5 | 19-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: Make arm_validate_ns_entrypoint() common
The function arm_validate_ns_entrypoint() validates a given non-secure
physical address. This function however specifically returns PSCI error
ARM platforms: Make arm_validate_ns_entrypoint() common
The function arm_validate_ns_entrypoint() validates a given non-secure
physical address. This function however specifically returns PSCI error
codes.
Non-secure physical address validation is potentially useful across ARM
platforms, even for non-PSCI use cases. Therefore make this function
common by returning 0 for success or -1 otherwise.
Having made the function common, make arm_validate_psci_entrypoint() a
wrapper around arm_validate_ns_entrypoint() which only translates return
value into PSCI error codes. This wrapper is now used where
arm_validate_ns_entrypoint() was currently used for PSCI entry point
validation.
Change-Id: Ic781fc3105d6d199fd8f53f01aba5baea0ebc310
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 058efeef | 07-Nov-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GICv2: Fix populating PE target data
This patch brings in the following fixes:
- The per-PE target data initialized during power up needs to be
flushed so as to be visible to other PEs.
-
GICv2: Fix populating PE target data
This patch brings in the following fixes:
- The per-PE target data initialized during power up needs to be
flushed so as to be visible to other PEs.
- Setup per-PE target data for the primary PE as well. At present,
this was only setup for secondary PEs when they were powered on.
Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 9500d5a4 | 09-Nov-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1148 from antonio-nino-diaz-arm/an/spm
Introduce Secure Partition Manager |
| e29efeb1 | 09-Nov-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
SPM: FVP: Introduce port of SPM
This initial port of the Secure Partitions Manager to FVP supports BL31
in both SRAM and Trusted DRAM.
A document with instructions to build the SPM has been added.
SPM: FVP: Introduce port of SPM
This initial port of the Secure Partitions Manager to FVP supports BL31
in both SRAM and Trusted DRAM.
A document with instructions to build the SPM has been added.
Change-Id: I4ea83ff0a659be77f2cd72eaf2302cdf8ba98b32
Co-authored-by: Douglas Raillard <douglas.raillard@arm.com>
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Achin Gupta <achin.gupta@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 92c5066c | 06-Nov-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1153 from robertovargas-arm/fix-macros
Avoid use of undefined macros |
| 3de7d58e | 03-Nov-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1137 from soby-mathew/sm/arm_plat_en_gicv3_save
Enable GICv3 save for ARM platforms |
| d58f3cac | 20-Oct-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
Always define ARM_TSP_RAM_LOCATION_ID
ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro
was also used in AARCH32, and it meant that it was taking the value 0,
which happened to equa
Always define ARM_TSP_RAM_LOCATION_ID
ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro
was also used in AARCH32, and it meant that it was taking the value 0,
which happened to equal ARM_TRUSTED_SRAM_ID.
Change-Id: If9f4dbee1a2ba15e7806f2a03305b554bd327363
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
show more ...
|
| 7ca267bd | 13-Oct-2017 |
Qixiang Xu <qixiang.xu@arm.com> |
plat/arm: change the default option of ARM_TSP_RAM_LOCATION
On Arm standard platforms, it runs out of SRAM space when TBB is
enabled, so the TSP default location is changed to dram when TBB
is enabl
plat/arm: change the default option of ARM_TSP_RAM_LOCATION
On Arm standard platforms, it runs out of SRAM space when TBB is
enabled, so the TSP default location is changed to dram when TBB
is enabled.
Change-Id: I516687013ad436ef454d2055d4e6fce06e467044
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
show more ...
|
| b2c363b1 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: Migrate to using interrupt properties
An earlier patch added provision for the platform to provide secure
interrupt properties. ARM platforms already has a list of interrupts
that fal
ARM platforms: Migrate to using interrupt properties
An earlier patch added provision for the platform to provide secure
interrupt properties. ARM platforms already has a list of interrupts
that fall into different secure groups.
This patch defines macros that enumerate interrupt properties in the
same fashion, and points the driver driver data to a list of interrupt
properties rather than list of secure interrupts on ARM platforms. The
deprecated interrupt list definitions are however retained to support
legacy builds.
Configuration applied to individual interrupts remain unchanged, so no
runtime behaviour change expected.
NOTE: Platforms that use the arm/common function
plat_arm_gic_driver_init() must replace their PLAT_ARM_G1S_IRQS and
PLAT_ARM_G0_IRQS macro definitions with PLAT_ARM_G1S_IRQ_PROPS and
PLAT_ARM_G0_IRQ_PROPS macros respectively, using the provided
INTR_PROP_DESC macro.
Change-Id: I24d643b83e3333753a3ba97d4b6fb71e16bb0952
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| dea417cd | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: supply per-PE target mask array
Call the GICv2 driver API to initialise per-PE target mask.
Change-Id: Idc7eb0d906a5379f4c05917af05c90613057ab97
Signed-off-by: Jeenu Viswambharan <je
ARM platforms: supply per-PE target mask array
Call the GICv2 driver API to initialise per-PE target mask.
Change-Id: Idc7eb0d906a5379f4c05917af05c90613057ab97
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| e35a3fb5 | 11-Oct-2017 |
Soby Mathew <soby.mathew@arm.com> |
ARM platforms: enable GICv3 state save/restore
Provides GICv3 save/restore feature to arm_system_pwr_domain_resume and
arm_system_pwr_domain_save functions.
Introduce FVP PSCI power level 3 (System
ARM platforms: enable GICv3 state save/restore
Provides GICv3 save/restore feature to arm_system_pwr_domain_resume and
arm_system_pwr_domain_save functions.
Introduce FVP PSCI power level 3 (System level) support. This is solely
done to provide example code on how to use the GICv3 save and restore
helpers.
Also make CSS GICv3 platforms power off the Redistributor on SYSTEM
SUSPEND as its state is saved and restored.
Change-Id: I0d852f3af8824edee1a17c085cf593ddd33a4e77
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Co-Authored-by: Douglas Raillard <douglas.raillard@arm.com>
show more ...
|