feat(rdaspen): add BL31 for RD-Aspen platform

Implement BL31 for RD-Aspen platform.

* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL ima

feat(rdaspen): add BL31 for RD-Aspen platform

Implement BL31 for RD-Aspen platform.

* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL image information that gets
used by BL2 to load the images

Change-Id: I5f389c4a6ef9bc106b3b29c9aecbd890d91d99b3
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

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feat(arm): implement arm platform GPT logging

The arm platform specific implementation of
logging corrupted primary GPT.

Change-Id: I73127668bcbf80e8fd2556da582fdcfc9ff9d524
Signed-off-by: Xialin L

feat(arm): implement arm platform GPT logging

The arm platform specific implementation of
logging corrupted primary GPT.

Change-Id: I73127668bcbf80e8fd2556da582fdcfc9ff9d524
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpufeat): add ras files to the build from a common location

If ENABLE_FEAT_RAS is unset on the build commandline the platform.mk
will run and make its decisions with the flag unset, after which

fix(cpufeat): add ras files to the build from a common location

If ENABLE_FEAT_RAS is unset on the build commandline the platform.mk
will run and make its decisions with the flag unset, after which
arch_features.mk will run and enable the feature. The result in the RAS
case is a build failure due to missing symbols.

Nvidia works around this by setting ENABLE_FEAT_RAS manually despite the
arch_features.mk setting.

Every platform that enables ENABLE_FEAT_RAS also pulls in
std_err_record.c and ras_common.c. So fix the build failure by having
these files be pulled into the build from common code in bl31.mk.

Change-Id: I018869d3f1904821523ac88d70e88eb90959784b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whet

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whether the platform might want to use something different. The thinking
was to provide a default and then let each platform override it, however
the order was swapped.

To fix this, put the gic_set_gicr_frames() in bl31_platform_setup()
rather than arm_bl31_platform_setup(). This way, platforms that use the
default can still enjoy it automatically pulled in from common code,
platforms that need fully custom gicr_frames can simply set it, and
platforms that override bl31_platform_setup() for unrelated reasons only
have to redo the call to gic_set_gicr_frames(). This has a tiny benefit
over the old approach in that there will never be 2 gicr_frames arrays.

Change-Id: I734737d3bd37ddbb3286abcdd92c88676c68cdc3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(arm): handle RMM ep_info during LFA

Update the logic for next image handoff to correctly manage the
RMM entry point information when LFA is in progress.
This ensures control is passed back into

feat(arm): handle RMM ep_info during LFA

Update the logic for next image handoff to correctly manage the
RMM entry point information when LFA is in progress.
This ensures control is passed back into RMM during the
activation sequence.

This change only affects during LFA run, normal boot behavior
is unchanged.

Change-Id: I8f85e9a7e0a7e9dab196c69ecf55abb9e7717982
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition table at
runtime, so a fixed offset is unnecessary. Also cleaned up the FIP
address handling comment for clarity.

Change-Id: I03f003a9307d66d16666eefcff1f45bb010779c9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, an

build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, and platform integration logic to link with lib as a
static library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibEventLog is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I723f493033c178759a45ea04118e7cc295dc2438
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SP

Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry
feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
feat(spmd): get spmc manifest from xferlist

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feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry

For compatibility with SPMCs that obtain
event log information from DT_SPMC_MANIFEST,
ensure the event log is updated when TF-A

feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry

For compatibility with SPMCs that obtain
event log information from DT_SPMC_MANIFEST,
ensure the event log is updated when TF-A uses firmware handoff.

Change-Id: Iafc11c63c86c2ee67481e3085d2e8390d5f99cea
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(spmd): get spmc manifest from xferlist

When TRANSFER_LIST build option is used, arg0 doesn't pass the
SPMC manifest. but it should be passed to load SPMC.

For this, adds the spmc manifest entr

feat(spmd): get spmc manifest from xferlist

When TRANSFER_LIST build option is used, arg0 doesn't pass the
SPMC manifest. but it should be passed to load SPMC.

For this, adds the spmc manifest entry in the transfer list
with TL_TAG_DT_SPMC_MANIFEST tag and
let spmd load the spmc manifest from transfer list.

Change-Id: I3b84c3d8a17bba4ac94afe00e1e19044449360b0
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONF

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONFIG_ADDR` with a common macro `ARM_HW_CONFIG_ADDR` for
accessing the device tree blob base address.

For FVP the DT address is set to use `ARM_PRELOADED_DTB_BASE` if
provided, falling back to a default address otherwise.

This provides a consistent mechanism for Arm platforms to define and
override the DTB base address used during kernel handoff. It reduces the
chance of misconfiguration, and simplifies platform integration.

Change-Id: Ib668dbb1de9d42cf41c0b0ee9a316f054891752a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "fix(arm): increase reserved DRAM1 mem for NS images" into integration

Merge "fix(arm): re-enable console by default in BL31" into integration

fix(arm): increase reserved DRAM1 mem for NS images

Defconfig kernels are now approaching 50MB, making the previous 64MB
allocation for both the kernel and initrd insufficient. To accommodate
this g

fix(arm): increase reserved DRAM1 mem for NS images

Defconfig kernels are now approaching 50MB, making the previous 64MB
allocation for both the kernel and initrd insufficient. To accommodate
this growth, increase the reserved NS memory to 128MB.

Change-Id: Ifffdda4623ec7930e4c830a6a222933807d09882
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "fix(drtm): remove plat_system_reset()" into integration

Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declar

Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declare unused parameters as void

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fix(arm): re-enable console by default in BL31

In c997a8d, the common `arm_bl31_early_platform_setup` function
underwent a consolidation of two large preprocessor branches that were
conditional on w

fix(arm): re-enable console by default in BL31

In c997a8d, the common `arm_bl31_early_platform_setup` function
underwent a consolidation of two large preprocessor branches that were
conditional on whether or not Transfer List support is enabled.

This function would initialise the console via `arm_console_boot_init`
*only* if Transfer List support was disabled. During the consolidation,
this call was removed, such that the behaviour was the same for both
branches.

However, the common `bl31_early_platform_setup2` implementation was not
updated to reflect this change, and so platforms that a) relied on this
common implementation and b) did not enable Transfer List support no
longer initialise the console in BL31.

This change ensures that the common implementation correctly initialises
the console during early BL31 boot.

Change-Id: I332af3932ac70382fbf7a5434c0008807f38f86c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that i

fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that is only implemented on FVP, that conflicts with it.
This sometimes results in failed builds.

DRTM remediation ends with a platform reset. However, there is currently
an error message printed that this is not supported. In this case, the
correct thing to do is to panic and as such this hook is not needed.

Further, the correct sequence to reset the system is different and is
only fully implemented by psci_system_reset(). This is a portable
implementation supported by a wide variety of platform.

So remove plat_system_reset(). Once DRTM remediation properly supports
resetting, the psci_system_reset() function should be used to achieve
reset correctly and portably.

Change-Id: Ia4e150c51aeec613838464fbb0e1d0542f19ccab
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(bl31): remove incorrect asserts

When RESET_TO_BL31 is defined, BL31 is the reset vector and no
parameters are provided by a previous bootloader.
Therefore, the arguments arg0 to arg3 passed to
a

fix(bl31): remove incorrect asserts

When RESET_TO_BL31 is defined, BL31 is the reset vector and no
parameters are provided by a previous bootloader.
Therefore, the arguments arg0 to arg3 passed to
arm_bl31_early_platform_setup() must be ignored.
They come directly from the BL31 entrypoint.
The GP registers reset to an architecturally unknown value
so are not necessarily initialized to zero.

Signed-off-by: Alexandre Gonzalo <alexandre.gonzalo@arm.com>
Change-Id: I38dde35145f2bd27fe9645906df192b138984c1d

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces

refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces duplication and simplifies control over SPSR
generation for later stages, particularly BL33.

The SPD remains responsible for setting the SPSR for BL32.

Change-Id: Ibbba708d607e7676989f5c7ceffe33d7bb2195f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Document

feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Documentation/arm64/booting.rst.

In addition:

- Clean up legacy ARM_LINUX_KERNEL_AS_BL33 handling since
USE_KERNEL_DT_CONVENTION now implies this mode for DT handoff.
- Override args.arg0 for BL33 to point to ARM_PRELOADED_DTB_BASE in
RESET_TO_BL31.
- Skip setting the primary MPID in x0 when using this convention.

Change-Id: Ieea8cfe68104b82038b9311613abf13afe7b48f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3

Load tos_fw_cfg when SPMC_AT_EL3 enabled and deliver its manifest
via transfer list and set its address in entrypoint's arg0 to load it
prope

feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3

Load tos_fw_cfg when SPMC_AT_EL3 enabled and deliver its manifest
via transfer list and set its address in entrypoint's arg0 to load it
properly by spmc_setup().

Change-Id: I43490d0bbe8288701efcce93313838395d41f330
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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