| 572c8ce2 | 15-Sep-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
feat(morello): add DTS for Morello SoC platform
Added Morello SoC specific DTS file.
Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Signed-of
feat(morello): add DTS for Morello SoC platform
Added Morello SoC specific DTS file.
Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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| 9b8c431e | 30-Nov-2021 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
feat(morello): configure DMC-Bing mode
Based on the SCC configuration value obtained from the SDS platform information structure configure DMC-Bing Server or Client mode after zeroing out the memory
feat(morello): configure DMC-Bing mode
Based on the SCC configuration value obtained from the SDS platform information structure configure DMC-Bing Server or Client mode after zeroing out the memory.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Change-Id: I0555fa06c9c1906264848f4e32ca413b4742cdee
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| 2d39b397 | 26-Aug-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
feat(morello): zero out the DDR memory space
For Morello SoC, we use ECC capability for the RDIMMs which require the entire DDR memory space to be zeroed out before it can be accessed.
Change-Id: I
feat(morello): zero out the DDR memory space
For Morello SoC, we use ECC capability for the RDIMMs which require the entire DDR memory space to be zeroed out before it can be accessed.
Change-Id: Icbe9916f9a2d3c4ce839d8bf7f867efa18f33e23 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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