fix(morello): change the AP runtime UART address

SoC UART1 is internally connected to MCP UART1 so this
cannot be used as AP runtime UART instead we use the
IOFPGA UART0 as the AP runtime UART.

Sig

fix(morello): change the AP runtime UART address

SoC UART1 is internally connected to MCP UART1 so this
cannot be used as AP runtime UART instead we use the
IOFPGA UART0 as the AP runtime UART.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: Iecefb0d2cb875b3ecf97e0983b06f6e914835021

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feat(morello): add support for nt_fw_config

This patch adds support to load nt_fw_config
with the information from plat_info sds
structure which is then passed from BL2 to BL33.

Signed-off-by: sah0

feat(morello): add support for nt_fw_config

This patch adds support to load nt_fw_config
with the information from plat_info sds
structure which is then passed from BL2 to BL33.

Signed-off-by: sah01 <sahil@arm.com>
Change-Id: I2242da7404c72a4f9c2e3d7f3b5c154890a78526

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feat(morello): split platform_info sds struct

Different platform_info sds struct definition will be used
for fvp and soc.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I92f0e1b2d0d755ad0405ceebfe

feat(morello): split platform_info sds struct

Different platform_info sds struct definition will be used
for fvp and soc.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I92f0e1b2d0d755ad0405ceebfeb78d6e4c67013d

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feat(morello): add changes to enable TBBR boot

This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.

Signed-off-by: sahil <sahil@arm.com>
Change-Id

feat(morello): add changes to enable TBBR boot

This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ib8f7f326790b13082cbe8db21a980e048e3db88c

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feat(morello): add DTS for Morello SoC platform

Added Morello SoC specific DTS file.

Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-of

feat(morello): add DTS for Morello SoC platform

Added Morello SoC specific DTS file.

Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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feat(morello): configure DMC-Bing mode

Based on the SCC configuration value obtained from the SDS
platform information structure configure DMC-Bing Server or
Client mode after zeroing out the memory

feat(morello): configure DMC-Bing mode

Based on the SCC configuration value obtained from the SDS
platform information structure configure DMC-Bing Server or
Client mode after zeroing out the memory.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I0555fa06c9c1906264848f4e32ca413b4742cdee

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feat(morello): zero out the DDR memory space

For Morello SoC, we use ECC capability for the RDIMMs
which require the entire DDR memory space to be zeroed
out before it can be accessed.

Change-Id: I

feat(morello): zero out the DDR memory space

For Morello SoC, we use ECC capability for the RDIMMs
which require the entire DDR memory space to be zeroed
out before it can be accessed.

Change-Id: Icbe9916f9a2d3c4ce839d8bf7f867efa18f33e23
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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feat(morello): add TARGET_PLATFORM flag

The same folder "plat/arm/board/morello" is going to be
used by both Morello FVP and Morello SoC platforms.

TARGET_PLATFORM build flag has been introduced to

feat(morello): add TARGET_PLATFORM flag

The same folder "plat/arm/board/morello" is going to be
used by both Morello FVP and Morello SoC platforms.

TARGET_PLATFORM build flag has been introduced to
differentiate between the two platforms

Change-Id: I3e94da372a3f1ba810b4259b85dd4c204306c359
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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morello: Modify morello_plat_info structure

The structure has been modified to specify the memory
size in bytes instead of Gigabytes.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by

morello: Modify morello_plat_info structure

The structure has been modified to specify the memory
size in bytes instead of Gigabytes.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I3384677d79af4f3cf55d3c353b6c20bb827b5ae7

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rainier: remove cpu workaround for errata 1542419

This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.

Change-Id: Icaca299b13ef83

rainier: remove cpu workaround for errata 1542419

This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.

Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

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morello: Add changes to fix build of Morello Platform

This patch makes changes required to get the morello
platform working with the tip of TF-A.

Change-Id: I095006615c9959bba49fcc75b52e1de7d748630

morello: Add changes to fix build of Morello Platform

This patch makes changes required to get the morello
platform working with the tip of TF-A.

Change-Id: I095006615c9959bba49fcc75b52e1de7d7486309
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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plat/arm: Add platform support for Morello

This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to t

plat/arm: Add platform support for Morello

This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to take
the role of primary bootloader.

Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Anurag Koul <anurag.koul@arm.com>

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