feat(fvp): increase BL1 RW for PSA Crypto

Increase BL1 RW for PSA Crypto due to PSA key ID management redesign
needing an increase in heap size.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeiste

feat(fvp): increase BL1 RW for PSA Crypto

Increase BL1 RW for PSA Crypto due to PSA key ID management redesign
needing an increase in heap size.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I7c8d009f244be6252eff0d3ded3f1ca83fb1de21

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chore(fvp): remove unused macro definition

Remove an unused macro from the FVP platform code to
reduce clutter.

Change-Id: I88f9b3e6567362c0559fa58e1fbf9ace49c986b6
Signed-off-by: Manish V Badarkhe

chore(fvp): remove unused macro definition

Remove an unused macro from the FVP platform code to
reduce clutter.

Change-Id: I88f9b3e6567362c0559fa58e1fbf9ace49c986b6
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fvp): port event log to firmware handoff

Support handing off the event log to both the secure and non-secure
worlds using the firmware handoff framework. This also needs us to
increase the maxi

feat(fvp): port event log to firmware handoff

Support handing off the event log to both the secure and non-secure
worlds using the firmware handoff framework. This also needs us to
increase the maximum allocation for TB-FW configuration to accommodate
trusted boot entries.

Change-Id: I39d69d79434a366096dcf4fbdc5c434950170b78
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): increase bl2 mmap len for handoff

With firmware handoff and OP-TEE the BL2 translation tables need to be
one entry longer than they currently are. Increase the current max
length by this

feat(fvp): increase bl2 mmap len for handoff

With firmware handoff and OP-TEE the BL2 translation tables need to be
one entry longer than they currently are. Increase the current max
length by this much to allow to build these two configurations together.

Change-Id: Ibb7a62e1ded1aded072bc248a08f008f1b286c45
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): support AArch32 booting with handoff

Enable AArch32 SP_MIN booting on the FVP platform using Firmware
Handoff. Update plat_arm_sp_min_early_platform_setup() to parse boot
arguments passed

feat(fvp): support AArch32 booting with handoff

Enable AArch32 SP_MIN booting on the FVP platform using Firmware
Handoff. Update plat_arm_sp_min_early_platform_setup() to parse boot
arguments passed via the Firmware Handoff framework.

Also, adjust the maximum BL32 size calculation to use
PLAT_ARM_FW_HANDOFF_SIZE when TRANSFER_LIST is enabled.

Change-Id: I82032b1cebf8b37ff24dde4f2d07f7aaede33eb6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB

feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB of PCIe memory region 1 and 3GB of
PCIe memory region 2 to FVP PAS regions array.

Change-Id: Icadd528576f53c55b5d461ff4dcd357429ba622a
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is c

feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is controlled
by 'RME_GPT_BITLOCK_BLOCK' build option and 'PLAT_ARM_PPS'
macro defined in platform_def.h which specifies the size
of protected physical address space in bytes.
'PLAT_ARM_PPS' takes values from 4GB to 4PB supported by
Arm architecture.

Change-Id: Icf620b5039e45df6828d58fca089cad83b0bc669
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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chore(gpt): define PPS in platform header files

Define protected physical address size in bytes
PLAT_ARM_PPS macro for FVP and RDV3 in platform_def.h
files.

Change-Id: I7f6529dfbb8df864091fbefc0813

chore(gpt): define PPS in platform header files

Define protected physical address size in bytes
PLAT_ARM_PPS macro for FVP and RDV3 in platform_def.h
files.

Change-Id: I7f6529dfbb8df864091fbefc08131a0e6d689eb6
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Upda

feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Update RMMD_MANIFEST_VERSION_MINOR from 3 to 4.
- Read PCIe related information from DTB and write it to
Boot manifest.
- Rename structures that used to describe DRAM layout
and now describe both DRAM and PCIe IO memory regions:
- ns_dram_bank -> memory_bank
- ns_dram_info -> memory_info.

Change-Id: Ib75d1af86076f724f5c330074e231f1c2ba8e21d
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(fvp): define single Root region

For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library a

feat(fvp): define single Root region

For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library and use GPT
mapping with Contiguous descriptor of
larger block size.

Change-Id: I70f6babaebc14e5e0bce033783ec423c8a26c542
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(fvp): add StandaloneMm manifest in fvp

Support StandaloneMm running with FF-A as S-EL0 SP
when TF-A is built with EL3 SPMC partition manager.

For this
1. add manifest file describing Stand

feat(fvp): add StandaloneMm manifest in fvp

Support StandaloneMm running with FF-A as S-EL0 SP
when TF-A is built with EL3 SPMC partition manager.

For this
1. add manifest file describing StandaloneMm partition.
2. add number of page mapping area.
3. StandaloneMm should use SRAM with 512K.

while enabling, StandaloneMm, BL1 image requires more size:
aarch64-none-elf/bin/ld: BL31 image has exceeded its limit.
aarch64-none-elf/bin/ld: region `RAM' overflowed by 16384 bytes

So, when using SRAM size with 512K configuration,
increase size limit of BL1 binary.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Idaa1db510340ebb812cfd13588610b2eea941918

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feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up

feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up integration of TLC into the build system.

Change-Id: I4466e27a457dfd5bf709dc3a360a2b63bf6030ce
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): scale SP_MIN max size based on SRAM size

The maximum size for SP_MIN in the FVP is currently
fixed and does not scale with the SRAM size.
This update adjusts the SP_MIN size according to

feat(fvp): scale SP_MIN max size based on SRAM size

The maximum size for SP_MIN in the FVP is currently
fixed and does not scale with the SRAM size.
This update adjusts the SP_MIN size according to
the SRAM size used to build the FVP platform.

Change-Id: I95527e8ae6f8a73c336ed4fe05ace5de86d8991d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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feat(fvp): allow SIMD context to be put in TZC DRAM

This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are all

feat(fvp): allow SIMD context to be put in TZC DRAM

This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are allocated in a separate section withtin the TZC DRAM space.

Change-Id: Idf3f232a7960a8f84f279d496c76953a6dad2009
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(arm): support FW handoff b/w BL2 & BL31

Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent m

feat(arm): support FW handoff b/w BL2 & BL31

Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent models. Load the HW_CONFIG as a TE along with entry point
parameters for BL31 execution.

Change-Id: I7c4c6e8353ca978a13520fb3e15fb2803f0f1d0e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both n

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both needing it, two copies of this file are made in Trusted DRAM and
SRAM. The copy in Trusted DRAM is a workaround stemming from memory
constraints in SRAM. We temporarily map the range of memory in Trusted
DRAM into BL31 to allow it to consume the configuration. In principle,
however, BL31 execution should be limited to SRAM, hence reduce the
maximum size of the HW_CONFIG to 16KB in order to accommodate it in
SRAM. This is possible since in practice, the HW_CONFIG on FVP is only
about 11KB.

Change-Id: Idb5dc0637b402562b7177a2b4e2464c4f3f67da7
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717

refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(el3-spmc): add datastore linker script markers

Datastore symbol used by EL3 SPMC is not relocated at
boot time when using ENABLE_PIE=1.
Use linker script markers instead of symbol.

Signed-off-b

fix(el3-spmc): add datastore linker script markers

Datastore symbol used by EL3 SPMC is not relocated at
boot time when using ENABLE_PIE=1.
Use linker script markers instead of symbol.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: If22d2fc8deacc74c73d7dc51bb70093935d9fa2b

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fix(bl2): make BL2 SRAM footprint flexible

On FVP's the default SRAM size is severly restrictive. However, more
recent models support larger SRAM configurations (> 256 Kb). We
introduced the flag FV

fix(bl2): make BL2 SRAM footprint flexible

On FVP's the default SRAM size is severly restrictive. However, more
recent models support larger SRAM configurations (> 256 Kb). We
introduced the flag FVP_TRUSTED_SRAM_SIZE to allow for TF to handle
different configurations.

BL31 automatically benefits from this optimisation since it starts from
the bottom of shared memory, and runs up to the end of SRAM. Increase
the size of all BL2 builds in proportion to FVP_TRUSTED_SRAM_SIZE so
that BL2 covers around a third of SRAM.

Change-Id: Idf37e8cb86507ea44b97ac8b3b90fffefe13f57a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): delegate FFH RAS handling to SP

This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.

The detaile

feat(fvp): delegate FFH RAS handling to SP

This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.

The detailed steps are documented as comments in the relevant source
files introduced in this patch.

Change-Id: I97737c66649f6e49840fa0bdf2e0af4fb6b08fc7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(arm): retrieve GPT related data from platform

For RME-enabled platforms, initializing L0 and L1 tables and enabling
GPC checks is necessary. For systems using BL2 to load firmware images,
the G

feat(arm): retrieve GPT related data from platform

For RME-enabled platforms, initializing L0 and L1 tables and enabling
GPC checks is necessary. For systems using BL2 to load firmware images,
the GPT initialization has to be done in BL2 prior to the image load.
The common Arm platform code currently implements this in the
"arm_bl2_plat_gpt_setup" function, relying on the FVP platform's
specifications (PAS definitions, GPCCR_PPS, and GPCCR_PGS).

Different Arm platforms may have distinct PAS definitions, GPCCR_PPS,
GPCCR_PGS, L0/L1 base, and size. To accommodate these variations,
introduce the "plat_arm_get_gpt_info" API. Platforms must implement
this API to provide the necessary data for GPT setup on RME-enabled
platforms. It is essential to note that these additions are relevant to
platforms under the plat/arm hierarchy that will reuse the
"arm_bl2_plat_gpt_setup" function.

As a result of these new additions, migrate data related to the FVP
platform to its source and header files.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I4f4c8894c1cda0adc1f83e7439eb372e923f6147

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