Merge "fix(security): Set MDCR_EL3.MCCD bit" into integration

fix: random typos in tf-a code base

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id610f7e4398e799a2fbd74861274fd684c32db53

fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs

This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.

Signed-off-by: John

fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs

This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195

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fix(security): Set MDCR_EL3.MCCD bit

This patch adds setting MDCR_EL3.MCCD in 'el3_arch_init_common'
macro to disable cycle counting by PMCCNTR_EL0 in EL3 when
FEAT_PMUv3p7 is implemented. This fixe

fix(security): Set MDCR_EL3.MCCD bit

This patch adds setting MDCR_EL3.MCCD in 'el3_arch_init_common'
macro to disable cycle counting by PMCCNTR_EL0 in EL3 when
FEAT_PMUv3p7 is implemented. This fixes failing test
'Leak PMU CYCLE counter values from EL3 on PSCI suspend SMC'
on FVP models with 'has_v8_7_pmu_extension' parameter set to
1 or 2.

Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I2ad3ef501b31ee11306f76cb5a61032ecfd0fbda

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Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration

* changes:
stm32mp1: enable PIE for BL32
stm32mp1: set BL sizes regardless of flags
Add PIE support for AARCH32
Avoid t

Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration

* changes:
stm32mp1: enable PIE for BL32
stm32mp1: set BL sizes regardless of flags
Add PIE support for AARCH32
Avoid the use of linker *_SIZE__ macros

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Merge changes I36e45c0a,I69c21293 into integration

* changes:
plat/qemu: add "max" cpu support
Add support for QEMU "max" CPU

Add PIE support for AARCH32

Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done

Add PIE support for AARCH32

Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done for
PIE support on AARCH64.
The RELA_SECTION is redefined for AARCH32, as the created section is
.rel.dyn and the symbols are .rel*.

Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Add "_arm" suffix to Makalu ELP CPU lib

ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from othe

Add "_arm" suffix to Makalu ELP CPU lib

ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from other future versions.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20

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Add support for QEMU "max" CPU

Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.

Chang

Add support for QEMU "max" CPU

Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.

Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

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Merge "lib/cpu: Workaround for Cortex A77 erratum 1946167" into integration

Merge "Fix: Remove save/restore of EL2 timer registers" into integration

Fix: Remove save/restore of EL2 timer registers

Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following register

Fix: Remove save/restore of EL2 timer registers

Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
cnthps_ctl_el2
cnthps_tval_el2
cnthps_cval_el2
cnthvs_ctl_el2
cnthvs_tval_el2
cnthvs_cval_el2
cnthp_ctl_el2
cnthp_cval_el2
cnthp_tval_el2
cnthv_ctl_el2
cnthv_cval_el2
cnthv_tval_el2

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b

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lib/cpu: Workaround for Cortex A77 erratum 1946167

Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomi

lib/cpu: Workaround for Cortex A77 erratum 1946167

Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomic instructions without release semantics through a series of
writes to implementation defined system registers.

SDEN can be found here:
https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token=

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f

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Add Cortex_A78C CPU lib

Add basic support for Cortex_A78C CPU.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56

Add Makalu ELP CPU lib

Add basic support for Makalu ELP processor core.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93

cpus: add Matterhorn ELP ARM cpu library

Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607
Signed-off-by: Usama Arif <usama.arif@arm.com>

Merge "Add Makalu CPU lib" into integration

Merge "lib/extensions/ras: fix bug of binary search" into integration

Add Makalu CPU lib

Add basic support for Makalu CPU.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d

Enable v8.6 AMU enhancements (FEAT_AMUv1p1)

ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3

Enable v8.6 AMU enhancements (FEAT_AMUv1p1)

ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3 firmware.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217

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libc: memset: Fix MISRA issues

MISRA complained about "0"s not being followed by an "U" (please note
my protest about this!) and about values not being explicitly compared
to 0 (fair enough).
Also u

libc: memset: Fix MISRA issues

MISRA complained about "0"s not being followed by an "U" (please note
my protest about this!) and about values not being explicitly compared
to 0 (fair enough).
Also use explicit pointer types.

Fix those issues to make the CI happy.

Change-Id: I4d11e49c14f16223a71c78b0fc3e68ba9a1382d3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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lib: cpus: aarch32: sanity check pointers before use

This is the AARCH32 update of patch [1].

[1] 601e3ed209eb ("lib: cpus: sanity check pointers before use")

Signed-off-by: Yann Gautier <yann.ga

lib: cpus: aarch32: sanity check pointers before use

This is the AARCH32 update of patch [1].

[1] 601e3ed209eb ("lib: cpus: sanity check pointers before use")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I43dbe00a5802a7e1c6f877e22d1c66ec8275c6fa

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Merge changes from topic "mp/strto_libc" into integration

* changes:
libc: Import strtoull from FreeBSD project
libc: Import strtoll from FreeBSD project
libc: Import strtoul from FreeBSD proj

Merge changes from topic "mp/strto_libc" into integration

* changes:
libc: Import strtoull from FreeBSD project
libc: Import strtoll from FreeBSD project
libc: Import strtoul from FreeBSD project
libc: Import strtol from FreeBSD project

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rainier: remove cpu workaround for errata 1542419

This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.

Change-Id: Icaca299b13ef83

rainier: remove cpu workaround for errata 1542419

This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.

Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

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libc: Import strtoull from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, t

libc: Import strtoull from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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